adder_tp.v

Verilog 编写的fir滤波器

module adder_tp;    //加法器测试模块
reg [7:0] xin1,xin2;    
wire [8:0] xout;
parameter DELY=100;
adder myadder(xin1,xin2,xout);
initial
begin xin1=0;xin2=0;
#DELY xin1=223;xin2=67;
#DELY xin1=155;xin2=74;
#DELY xin1=189;xin2=112;
#DELY xin1=99;xin2=85;
#(DELY*10) $finish;
end
initial $monitor($time,,,"xin1=%d xin2=%d xout=%d ",xin1,xin2,xout);
endmodule