partmul_tp.v

Verilog 编写的fir滤波器

module partmul_tp;  //部分积产生测试模块
reg [7:0] hin;   //
reg [8:0] x;
reg reset;
wire [9:0] part1,part2,part3,part4;
wire [7:0] temp;
parameter DELY=100;
partmul mypartmul(hin,x,reset,part1,part2,part3,part4,temp);  //调用部分积产生模块
initial
begin reset=1; 
#DELY reset=0; x=9'h63;
#DELY reset=1;
#DELY hin=8'b01101101;
#DELY hin=8'b10110110;
#DELY hin=8'b10101010;
#DELY hin=8'b01111010;
#(DELY*10) $finish;
end
initial $monitor($time,,,"hin=%d x=%d reset=%d part1=%d part2=%d part3=%d part4=%d temp=%d",hin,x,reset,part1,part2,part3,part4,temp);
endmodule