adders.v

来自「Verilog 编写的fir滤波器」· Verilog 代码 · 共 24 行

module adders(P1,P2,P3);
input[15:0] P1,P2;
output[15:0] P3;
wire cout1,cout2,cout3,cout4,cout5,cout6,cout7,cout8,cout9;
wire [3:0] out1,out2,out3,out4,out5,out6;
wire sel1,sel2;
wire m1,m2;

fouradder fouradder1(P1[3:0],P2[3:0],1'b0,P3[3:0],cout1);
fouradder fouradder2(P1[7:4],P2[7:4],1'b0,out1,cout2);
fouradder fouradder3(P1[7:4],P2[7:4],1'b1,out2,cout3);
fouradder fouradder4(P1[11:8],P2[11:8],1'b0,out3,cout4);
fouradder fouradder5(P1[11:8],P2[11:8],1'b1,out4,cout5);
fouradder fouradder6(P1[15:12],P2[15:12],1'b0,out5,cout6);
fouradder fouradder7(P1[15:12],P2[15:12],1'b1,out6,cout7);
or(m1,cout1,cout2);
and(sel1,m1,cout3);
twomux twomux1(out1,out2,cout1,P3[7:4]);
twomux twomux2(out3,out4,sel1,P3[11:8]);
or(m2,sel1,cout4);
and(sel2,m2,cout5);
twomux twomux3(out5,out6,sel2,P3[15:12]);
endmodule