controller_tp.v

Verilog 编写的fir滤波器

module controller_tp;  //控制器测试模块
reg reset; 
reg clk1,clk2; 
wire [3:0] n;
wire OE;
parameter DELY=100;
controller mycontroller(clk1,clk2,n,OE);  //调用控制器模块
always #(DELY/2) clk2=~clk2;  //使clk1为clk2的10倍
always #(5*DELY) clk1=~clk1;
initial
begin clk1=0;reset=1;clk2=0;
#DELY reset=0;
#DELY reset=1;   
#(DELY*50) $finish;
end
initial $monitor($time,,," clk1=%d clk2=%d n=%d OE=%d",clk1,clk2,n,OE);
endmodule