up.v

Verilog 编写的fir滤波器

module up(clk1,clk2,reset,n,xin,hin,P,x1,x2,x3,x4,h,OE);
input clk1,clk2,reset;
input[7:0] xin;
input[63:0] hin;
output[16:0] P;
output [127:0] x1;
output [7:0] x2,x3;
output [8:0] x4;
output [7:0] h;
output [3:0] n;
output OE;
controller controller1(clk1,clk2,n,OE);
shifter shifter1(clk1,reset,xin,x1);
mux mux1(reset,n,x1,x2,x3);
adder adder1(x2,x3,x4);
muxh muxh1(reset,n,hin,h);
multiple multiple1(h,n,x4,reset,P);
endmodule