twomux.v

Verilog 编写的fir滤波器

module twomux(xin1,xin2,sel,xout);
input [3:0] xin1,xin2;
input sel;
output [3:0] xout;
reg[3:0] xout;
always@(xin1 or xin2 or sel)
 begin
 case(sel)
   0:  xout=xin1;
   1:  xout=xin2;
   default: xout=4'bzzzz;
 endcase
end
endmodule