📄 jsq24.rpt
字号:
A: 5/ 96( 5%) 0/ 48( 0%) 9/ 48( 18%) 2/16( 12%) 7/16( 43%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\userwork\clock24\jsq24\jsq24.rpt
jsq24
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: e:\userwork\clock24\jsq24\jsq24.rpt
jsq24
** EQUATIONS **
cin : INPUT;
clk : INPUT;
datain0 : INPUT;
datain1 : INPUT;
datain2 : INPUT;
datain3 : INPUT;
en0 : INPUT;
en1 : INPUT;
-- Node name is 'co'
-- Equation name is 'co', type is output
co = _LC1_A20;
-- Node name is 'q00'
-- Equation name is 'q00', type is output
q00 = s0n0;
-- Node name is 'q01'
-- Equation name is 'q01', type is output
q01 = s0n1;
-- Node name is 'q02'
-- Equation name is 'q02', type is output
q02 = s0n2;
-- Node name is 'q03'
-- Equation name is 'q03', type is output
q03 = s0n3;
-- Node name is 'q10'
-- Equation name is 'q10', type is output
q10 = s1n0;
-- Node name is 'q11'
-- Equation name is 'q11', type is output
q11 = s1n1;
-- Node name is 'q12'
-- Equation name is 'q12', type is output
q12 = s1n2;
-- Node name is 'q13'
-- Equation name is 'q13', type is output
q13 = s1n3;
-- Node name is ':21' = 's0n0'
-- Equation name is 's0n0', location is LC7_A20, type is buried.
s0n0 = DFFE( _EQ001, GLOBAL( clk), !(GLOBAL( en0) & !datain0), !(GLOBAL( en0) & datain0), VCC);
_EQ001 = !cin & s0n0
# cin & !s0n0;
-- Node name is ':20' = 's0n1'
-- Equation name is 's0n1', location is LC1_A13, type is buried.
s0n1 = DFFE( _EQ002, GLOBAL( clk), !(GLOBAL( en0) & !datain1), !(GLOBAL( en0) & datain1), VCC);
_EQ002 = _LC6_A13
# !cin & s0n1;
-- Node name is ':19' = 's0n2'
-- Equation name is 's0n2', location is LC5_A13, type is buried.
s0n2 = DFFE( _EQ003, GLOBAL( clk), !(GLOBAL( en0) & !datain2), !(GLOBAL( en0) & datain2), VCC);
_EQ003 = _LC7_A13
# !cin & s0n2;
-- Node name is ':18' = 's0n3'
-- Equation name is 's0n3', location is LC4_A13, type is buried.
s0n3 = DFFE( _EQ004, GLOBAL( clk), !(GLOBAL( en0) & !datain3), !(GLOBAL( en0) & datain3), VCC);
_EQ004 = _LC8_A13
# !cin & s0n3;
-- Node name is ':25' = 's1n0'
-- Equation name is 's1n0', location is LC1_A18, type is buried.
s1n0 = DFFE( _LC3_A18, GLOBAL( clk), !(GLOBAL( en1) & !datain0), !(GLOBAL( en1) & datain0), VCC);
-- Node name is ':24' = 's1n1'
-- Equation name is 's1n1', location is LC6_A18, type is buried.
s1n1 = DFFE( _EQ005, GLOBAL( clk), !(GLOBAL( en1) & !datain1), !(GLOBAL( en1) & datain1), VCC);
_EQ005 = _LC8_A18
# !cin & s1n1;
-- Node name is ':23' = 's1n2'
-- Equation name is 's1n2', location is LC1_A22, type is buried.
s1n2 = DFFE( s1n2, GLOBAL( clk), !(GLOBAL( en1) & !datain2), !(GLOBAL( en1) & datain2), VCC);
-- Node name is ':22' = 's1n3'
-- Equation name is 's1n3', location is LC2_A22, type is buried.
s1n3 = DFFE( s1n3, GLOBAL( clk), !(GLOBAL( en1) & !datain3), !(GLOBAL( en1) & datain3), VCC);
-- Node name is '|LPM_ADD_SUB:194|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A13', type is buried
!_LC3_A13 = _LC3_A13~NOT;
_LC3_A13~NOT = LCELL( _EQ006);
_EQ006 = !s0n1
# !s0n0;
-- Node name is '~119~1'
-- Equation name is '~119~1', location is LC2_A18, type is buried.
-- synthesized logic cell
_LC2_A18 = LCELL( _EQ007);
_EQ007 = !s0n3
# s0n1
# !s0n0
# s1n1;
-- Node name is ':138'
-- Equation name is '_LC4_A18', type is buried
_LC4_A18 = LCELL( _EQ008);
_EQ008 = !_LC2_A18 & !_LC8_A22 & s1n0;
-- Node name is '~277~1'
-- Equation name is '~277~1', location is LC5_A18, type is buried.
-- synthesized logic cell
_LC5_A18 = LCELL( _EQ009);
_EQ009 = !_LC4_A18 & _LC7_A18 & !s1n1
# !_LC2_A13 & !_LC4_A18 & _LC7_A18;
-- Node name is ':277'
-- Equation name is '_LC8_A13', type is buried
_LC8_A13 = LCELL( _EQ010);
_EQ010 = _LC5_A18 & !s0n2 & s0n3
# !_LC3_A13 & _LC5_A18 & s0n3
# _LC3_A13 & _LC5_A18 & s0n2 & !s0n3;
-- Node name is ':283'
-- Equation name is '_LC7_A13', type is buried
_LC7_A13 = LCELL( _EQ011);
_EQ011 = !_LC3_A13 & _LC5_A18 & s0n2
# _LC3_A13 & _LC5_A18 & !s0n2;
-- Node name is ':289'
-- Equation name is '_LC6_A13', type is buried
_LC6_A13 = LCELL( _EQ012);
_EQ012 = _LC5_A18 & !s0n0 & s0n1
# _LC5_A18 & s0n0 & !s0n1;
-- Node name is '~444~1'
-- Equation name is '~444~1', location is LC8_A22, type is buried.
-- synthesized logic cell
_LC8_A22 = LCELL( _EQ013);
_EQ013 = s0n2
# s1n3
# s1n2;
-- Node name is ':444'
-- Equation name is '_LC2_A13', type is buried
!_LC2_A13 = _LC2_A13~NOT;
_LC2_A13~NOT = LCELL( _EQ014);
_EQ014 = !_LC3_A13
# s0n3
# s1n0
# _LC8_A22;
-- Node name is '~597~1'
-- Equation name is '~597~1', location is LC7_A18, type is buried.
-- synthesized logic cell
_LC7_A18 = LCELL( _EQ015);
_EQ015 = cin & s1n0
# cin & _LC8_A22
# cin & _LC2_A18;
-- Node name is ':597'
-- Equation name is '_LC8_A18', type is buried
_LC8_A18 = LCELL( _EQ016);
_EQ016 = _LC4_A18 & _LC7_A18
# !_LC2_A13 & _LC7_A18 & s1n1;
-- Node name is ':602'
-- Equation name is '_LC3_A18', type is buried
_LC3_A18 = LCELL( _EQ017);
_EQ017 = cin & !_LC2_A18 & !_LC8_A22 & !s1n0
# !cin & s1n0
# _LC8_A22 & s1n0
# _LC2_A18 & s1n0;
-- Node name is ':657'
-- Equation name is '_LC1_A20', type is buried
_LC1_A20 = LCELL( _EQ018);
_EQ018 = cin & _LC2_A13 & s1n1;
Project Information e:\userwork\clock24\jsq24\jsq24.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:01
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:07
Memory Allocated
-----------------
Peak memory allocated during compilation = 26,100K
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