📄 decoder.rpt
字号:
A: 2/ 96( 2%) 0/ 48( 0%) 7/ 48( 14%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\userwork\clock24\decoder.rpt
decoder
** EQUATIONS **
datain0 : INPUT;
datain1 : INPUT;
datain2 : INPUT;
datain3 : INPUT;
-- Node name is 'y0'
-- Equation name is 'y0', type is output
y0 = _LC4_A14;
-- Node name is 'y1'
-- Equation name is 'y1', type is output
y1 = _LC8_A14;
-- Node name is 'y2'
-- Equation name is 'y2', type is output
y2 = _LC1_A14;
-- Node name is 'y3'
-- Equation name is 'y3', type is output
y3 = _LC3_A21;
-- Node name is 'y4'
-- Equation name is 'y4', type is output
y4 = !_LC8_A21;
-- Node name is 'y5'
-- Equation name is 'y5', type is output
y5 = _LC5_A21;
-- Node name is 'y6'
-- Equation name is 'y6', type is output
y6 = _LC1_A21;
-- Node name is 'y7'
-- Equation name is 'y7', type is output
y7 = VCC;
-- Node name is ':322'
-- Equation name is '_LC4_A21', type is buried
!_LC4_A21 = _LC4_A21~NOT;
_LC4_A21~NOT = LCELL( _EQ001);
_EQ001 = datain3
# !datain1
# !datain0
# !datain2;
-- Node name is '~370~1'
-- Equation name is '~370~1', location is LC2_A14, type is buried.
-- synthesized logic cell
_LC2_A14 = LCELL( _EQ002);
_EQ002 = datain0 & datain1 & !datain3;
-- Node name is ':382'
-- Equation name is '_LC8_A21', type is buried
_LC8_A21 = LCELL( _EQ003);
_EQ003 = !datain0 & datain1 & !datain2 & !datain3;
-- Node name is ':394'
-- Equation name is '_LC5_A14', type is buried
!_LC5_A14 = _LC5_A14~NOT;
_LC5_A14~NOT = LCELL( _EQ004);
_EQ004 = datain2
# datain1
# !datain0
# datain3;
-- Node name is ':406'
-- Equation name is '_LC6_A14', type is buried
!_LC6_A14 = _LC6_A14~NOT;
_LC6_A14~NOT = LCELL( _EQ005);
_EQ005 = datain2
# datain1
# datain0
# datain3;
-- Node name is ':442'
-- Equation name is '_LC1_A21', type is buried
_LC1_A21 = LCELL( _EQ006);
_EQ006 = datain1
# datain3
# !datain0 & !datain2
# datain0 & datain2;
-- Node name is ':475'
-- Equation name is '_LC5_A21', type is buried
_LC5_A21 = LCELL( _EQ007);
_EQ007 = datain3
# !datain2
# !datain0 & !datain1
# datain0 & datain1;
-- Node name is ':541'
-- Equation name is '_LC3_A21', type is buried
_LC3_A21 = LCELL( _EQ008);
_EQ008 = datain3
# !datain0 & datain1
# datain1 & !datain2
# !datain0 & !datain2
# datain0 & !datain1 & datain2;
-- Node name is ':570'
-- Equation name is '_LC2_A21', type is buried
_LC2_A21 = LCELL( _EQ009);
_EQ009 = datain2 & datain3
# datain1 & datain3
# !datain1 & !datain2 & !datain3
# !datain0 & !datain2
# !datain0 & datain1
# !datain0 & datain3;
-- Node name is ':574'
-- Equation name is '_LC1_A14', type is buried
_LC1_A14 = LCELL( _EQ010);
_EQ010 = _LC2_A21 & !_LC5_A14
# !_LC5_A14 & _LC8_A21
# _LC6_A14;
-- Node name is ':607'
-- Equation name is '_LC8_A14', type is buried
_LC8_A14 = LCELL( _EQ011);
_EQ011 = !_LC3_A14 & !_LC4_A21 & !_LC5_A14
# _LC6_A14;
-- Node name is '~634~1'
-- Equation name is '~634~1', location is LC3_A14, type is buried.
-- synthesized logic cell
_LC3_A14 = LCELL( _EQ012);
_EQ012 = _LC8_A21
# !datain2 & _LC2_A14;
-- Node name is '~642~1'
-- Equation name is '~642~1', location is LC7_A14, type is buried.
-- synthesized logic cell
_LC7_A14 = LCELL( _EQ013);
_EQ013 = !datain1 & datain2 & !datain3
# !datain0 & datain2 & !datain3
# !datain1 & !datain2 & datain3;
-- Node name is ':642'
-- Equation name is '_LC4_A14', type is buried
_LC4_A14 = LCELL( _EQ014);
_EQ014 = _LC3_A14 & !_LC5_A14 & !_LC6_A14
# !_LC5_A14 & !_LC6_A14 & _LC7_A14;
Project Information e:\userwork\clock24\decoder.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:05
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:07
Memory Allocated
-----------------
Peak memory allocated during compilation = 27,297K
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