📄 clock24.rpt
字号:
Device-Specific Information: e:\userwork\clock24\clock24.rpt
clock24
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
82 - - C -- OUTPUT 0 1 0 0 co
46 - - - 17 OUTPUT 0 1 0 0 h00
100 - - A -- OUTPUT 0 1 0 0 h01
11 - - A -- OUTPUT 0 1 0 0 h02
12 - - A -- OUTPUT 0 1 0 0 h03
13 - - A -- OUTPUT 0 1 0 0 h04
7 - - A -- OUTPUT 0 1 0 0 h05
135 - - - 18 OUTPUT 0 1 0 0 h06
133 - - - 17 OUTPUT 0 0 0 0 h07
9 - - A -- OUTPUT 0 1 0 0 h10
141 - - - 22 OUTPUT 0 1 0 0 h11
140 - - - 21 OUTPUT 0 1 0 0 h12
14 - - A -- OUTPUT 0 1 0 0 h13
130 - - - 14 OUTPUT 0 1 0 0 h14
10 - - A -- OUTPUT 0 1 0 0 h15
39 - - - 21 OUTPUT 0 1 0 0 h16
37 - - - 23 OUTPUT 0 0 0 0 h17
101 - - A -- OUTPUT 0 1 0 0 m00
118 - - - 07 OUTPUT 0 1 0 0 m01
95 - - A -- OUTPUT 0 1 0 0 m02
97 - - A -- OUTPUT 0 1 0 0 m03
68 - - - 07 OUTPUT 0 1 0 0 m04
96 - - A -- OUTPUT 0 1 0 0 m05
98 - - A -- OUTPUT 0 1 0 0 m06
49 - - - 14 OUTPUT 0 0 0 0 m07
72 - - - 04 OUTPUT 0 1 0 0 m10
31 - - C -- OUTPUT 0 1 0 0 m11
83 - - C -- OUTPUT 0 1 0 0 m12
81 - - C -- OUTPUT 0 1 0 0 m13
79 - - C -- OUTPUT 0 1 0 0 m14
78 - - C -- OUTPUT 0 1 0 0 m15
80 - - C -- OUTPUT 0 1 0 0 m16
117 - - - 06 OUTPUT 0 0 0 0 m17
22 - - B -- OUTPUT 0 1 0 0 s00
23 - - B -- OUTPUT 0 1 0 0 s01
20 - - B -- OUTPUT 0 1 0 0 s02
21 - - B -- OUTPUT 0 1 0 0 s03
17 - - B -- OUTPUT 0 1 0 0 s04
18 - - B -- OUTPUT 0 1 0 0 s05
19 - - B -- OUTPUT 0 1 0 0 s06
120 - - - 09 OUTPUT 0 0 0 0 s07
33 - - C -- OUTPUT 0 1 0 0 s10
32 - - C -- OUTPUT 0 1 0 0 s11
28 - - C -- OUTPUT 0 1 0 0 s12
30 - - C -- OUTPUT 0 1 0 0 s13
27 - - C -- OUTPUT 0 1 0 0 s14
29 - - C -- OUTPUT 0 1 0 0 s15
26 - - C -- OUTPUT 0 1 0 0 s16
143 - - - 24 OUTPUT 0 0 0 0 s17
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\userwork\clock24\clock24.rpt
clock24
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - B 18 AND2 0 4 1 0 |decoder:u3|:382
- 2 - B 18 OR2 0 4 1 0 |decoder:u3|:442
- 1 - B 18 OR2 0 4 1 0 |decoder:u3|:475
- 8 - B 18 OR2 0 4 1 0 |decoder:u3|:541
- 3 - B 18 OR2 0 4 1 0 |decoder:u3|:574
- 7 - B 18 OR2 0 4 1 0 |decoder:u3|:607
- 6 - B 18 OR2 0 4 1 0 |decoder:u3|:642
- 1 - C 18 AND2 0 4 1 0 |decoder:u4|:382
- 4 - C 18 OR2 0 4 1 0 |decoder:u4|:442
- 3 - C 18 OR2 0 4 1 0 |decoder:u4|:475
- 5 - C 18 OR2 0 4 1 0 |decoder:u4|:541
- 2 - C 18 OR2 0 4 1 0 |decoder:u4|:574
- 6 - C 18 OR2 0 4 1 0 |decoder:u4|:607
- 7 - C 18 OR2 0 4 1 0 |decoder:u4|:642
- 3 - A 07 AND2 0 4 1 0 |decoder:u5|:382
- 5 - A 07 OR2 0 4 1 0 |decoder:u5|:442
- 7 - A 07 OR2 0 4 1 0 |decoder:u5|:475
- 6 - A 07 OR2 0 4 1 0 |decoder:u5|:541
- 8 - A 07 OR2 0 4 1 0 |decoder:u5|:574
- 4 - A 07 OR2 0 4 1 0 |decoder:u5|:607
- 2 - A 07 OR2 0 4 1 0 |decoder:u5|:642
- 5 - C 09 AND2 0 4 1 0 |decoder:u6|:382
- 4 - C 04 OR2 0 4 1 0 |decoder:u6|:442
- 7 - C 04 OR2 0 4 1 0 |decoder:u6|:475
- 2 - C 04 OR2 0 4 1 0 |decoder:u6|:541
- 1 - C 04 OR2 0 4 1 0 |decoder:u6|:574
- 6 - C 04 OR2 0 4 1 0 |decoder:u6|:607
- 5 - C 04 OR2 0 4 1 0 |decoder:u6|:642
- 2 - A 14 OR2 ! 0 4 0 2 |decoder:u7|:298
- 7 - A 16 OR2 ! 0 3 0 3 |decoder:u7|:370
- 7 - A 18 AND2 0 4 1 0 |decoder:u7|:382
- 8 - A 18 OR2 0 4 1 0 |decoder:u7|:442
- 1 - A 18 OR2 0 4 1 0 |decoder:u7|:475
- 6 - A 18 OR2 0 4 1 0 |decoder:u7|:541
- 5 - A 18 OR2 0 4 1 0 |decoder:u7|:574
- 2 - A 18 OR2 0 4 1 0 |decoder:u7|:607
- 3 - A 18 OR2 0 4 1 0 |decoder:u7|:642
- 5 - A 13 OR2 ! 0 2 1 2 |decoder:u8|:382
- 4 - A 14 OR2 ! 0 4 0 1 |decoder:u8|:394
- 1 - A 22 OR2 0 4 1 0 |decoder:u8|:442
- 3 - A 22 OR2 0 4 1 0 |decoder:u8|:475
- 8 - A 22 OR2 0 4 1 0 |decoder:u8|:541
- 6 - A 22 OR2 0 4 1 0 |decoder:u8|:574
- 7 - A 22 OR2 0 4 1 0 |decoder:u8|:607
- 2 - A 22 OR2 0 4 1 0 |decoder:u8|:642
- 4 - A 16 AND2 0 2 0 3 |jsq24:u2|LPM_ADD_SUB:194|addcore:adder|:55
- 1 - A 16 DFFE + 2 2 0 10 |jsq24:u2|s0n3 (|jsq24:u2|:18)
- 2 - A 16 DFFE + 2 2 0 11 |jsq24:u2|s0n2 (|jsq24:u2|:19)
- 3 - A 16 DFFE + 2 2 0 10 |jsq24:u2|s0n1 (|jsq24:u2|:20)
- 4 - A 18 DFFE + 2 1 0 10 |jsq24:u2|s0n0 (|jsq24:u2|:21)
- 5 - A 22 DFFE + 2 0 0 8 |jsq24:u2|s1n3 (|jsq24:u2|:22)
- 8 - A 14 DFFE + 2 0 0 8 |jsq24:u2|s1n2 (|jsq24:u2|:23)
- 1 - A 13 DFFE + 2 2 0 10 |jsq24:u2|s1n1 (|jsq24:u2|:24)
- 1 - A 14 DFFE + 2 1 0 9 |jsq24:u2|s1n0 (|jsq24:u2|:25)
- 4 - A 13 OR2 ! 0 3 0 3 |jsq24:u2|:119
- 3 - A 14 OR2 ! 0 2 0 3 |jsq24:u2|:138
- 6 - A 16 OR2 0 4 0 1 |jsq24:u2|:277
- 8 - A 13 AND2 s 0 2 0 1 |jsq24:u2|~283~1
- 5 - A 16 OR2 0 3 0 1 |jsq24:u2|:283
- 7 - A 13 OR2 s 0 4 0 3 |jsq24:u2|~289~1
- 8 - A 16 OR2 0 3 0 1 |jsq24:u2|:289
- 4 - A 22 OR2 s 0 3 0 3 |jsq24:u2|~444~1
- 3 - A 13 OR2 0 3 0 1 |jsq24:u2|:555
- 6 - A 13 OR2 0 4 0 1 |jsq24:u2|:597
- 2 - A 13 OR2 0 4 0 1 |jsq24:u2|:602
- 2 - C 02 AND2 0 4 1 0 |jsq24:u2|:657
- 8 - B 16 AND2 0 2 0 1 |jsq60:u0|LPM_ADD_SUB:94|addcore:adder|:55
- 8 - C 19 AND2 0 2 0 1 |jsq60:u0|LPM_ADD_SUB:267|addcore:adder|:55
- 5 - B 18 DFFE + 2 1 0 9 |jsq60:u0|s0n3 (|jsq60:u0|:18)
- 2 - B 13 DFFE + 2 1 0 10 |jsq60:u0|s0n2 (|jsq60:u0|:19)
- 1 - B 13 DFFE + 2 1 0 11 |jsq60:u0|s0n1 (|jsq60:u0|:20)
- 3 - B 13 DFFE + 2 0 0 11 |jsq60:u0|s0n0 (|jsq60:u0|:21)
- 8 - C 18 DFFE + 1 2 0 9 |jsq60:u0|s1n3 (|jsq60:u0|:22)
- 4 - C 19 DFFE + 1 2 0 10 |jsq60:u0|s1n2 (|jsq60:u0|:23)
- 3 - C 19 DFFE + 1 2 0 11 |jsq60:u0|s1n1 (|jsq60:u0|:24)
- 4 - B 16 DFFE + 2 1 0 11 |jsq60:u0|s1n0 (|jsq60:u0|:25)
- 6 - B 16 OR2 ! 0 4 0 3 |jsq60:u0|:69
- 7 - B 16 AND2 s 1 1 0 3 |jsq60:u0|~147~1
- 2 - B 16 OR2 0 4 0 1 |jsq60:u0|:147
- 5 - B 16 OR2 0 4 0 1 |jsq60:u0|:153
- 3 - B 16 OR2 0 3 0 1 |jsq60:u0|:159
- 1 - B 16 OR2 ! 1 1 0 6 |jsq60:u0|:232
- 1 - C 19 OR2 ! 0 4 0 3 |jsq60:u0|:242
- 5 - C 19 AND2 s 0 2 0 3 |jsq60:u0|~320~1
- 2 - C 19 OR2 0 4 0 1 |jsq60:u0|:320
- 6 - C 19 OR2 0 4 0 1 |jsq60:u0|:326
- 7 - C 19 OR2 0 3 0 1 |jsq60:u0|:332
- 1 - A 21 OR2 ! 0 2 0 5 |jsq60:u0|:392
- 1 - A 07 AND2 0 2 0 1 |jsq60:u1|LPM_ADD_SUB:94|addcore:adder|:55
- 8 - C 02 AND2 0 2 0 1 |jsq60:u1|LPM_ADD_SUB:267|addcore:adder|:55
- 3 - A 05 DFFE + 1 2 0 9 |jsq60:u1|s0n3 (|jsq60:u1|:18)
- 4 - A 05 DFFE + 1 2 0 10 |jsq60:u1|s0n2 (|jsq60:u1|:19)
- 2 - A 05 DFFE + 1 2 0 11 |jsq60:u1|s0n1 (|jsq60:u1|:20)
- 8 - A 17 DFFE + 1 2 0 11 |jsq60:u1|s0n0 (|jsq60:u1|:21)
- 2 - C 09 DFFE + 1 2 0 9 |jsq60:u1|s1n3 (|jsq60:u1|:22)
- 7 - C 02 DFFE + 1 2 0 10 |jsq60:u1|s1n2 (|jsq60:u1|:23)
- 3 - C 04 DFFE + 1 2 0 11 |jsq60:u1|s1n1 (|jsq60:u1|:24)
- 4 - C 09 DFFE + 1 1 0 11 |jsq60:u1|s1n0 (|jsq60:u1|:25)
- 1 - A 05 OR2 ! 0 4 0 2 |jsq60:u1|:69
- 5 - A 05 AND2 s 0 2 0 3 |jsq60:u1|~147~1
- 8 - A 05 OR2 0 4 0 1 |jsq60:u1|:147
- 6 - A 05 OR2 0 4 0 1 |jsq60:u1|:153
- 7 - A 05 OR2 0 3 0 1 |jsq60:u1|:159
- 1 - A 09 OR2 ! 0 2 0 7 |jsq60:u1|:232
- 4 - C 02 OR2 ! 0 4 0 3 |jsq60:u1|:242
- 3 - C 02 AND2 s 0 2 0 3 |jsq60:u1|~320~1
- 5 - C 02 OR2 0 4 0 1 |jsq60:u1|:320
- 6 - C 02 OR2 0 4 0 1 |jsq60:u1|:326
- 8 - C 04 OR2 0 3 0 1 |jsq60:u1|:332
- 1 - C 02 OR2 ! 0 2 0 8 |jsq60:u1|:392
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\userwork\clock24\clock24.rpt
clock24
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 13/ 96( 13%) 10/ 48( 20%) 22/ 48( 45%) 2/16( 12%) 13/16( 81%) 0/16( 0%)
B: 5/ 96( 5%) 0/ 48( 0%) 16/ 48( 33%) 1/16( 6%) 7/16( 43%) 0/16( 0%)
C: 6/ 96( 6%) 13/ 48( 27%) 13/ 48( 27%) 0/16( 0%) 14/16( 87%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\userwork\clock24\clock24.rpt
clock24
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 24 clk
Device-Specific Information: e:\userwork\clock24\clock24.rpt
clock24
** EQUATIONS **
cin : INPUT;
clk : INPUT;
datain0 : INPUT;
datain1 : INPUT;
datain2 : INPUT;
datain3 : INPUT;
en0 : INPUT;
en1 : INPUT;
en2 : INPUT;
en3 : INPUT;
en4 : INPUT;
en5 : INPUT;
-- Node name is 'co'
-- Equation name is 'co', type is output
co = _LC2_C2;
-- Node name is 'h00'
-- Equation name is 'h00', type is output
h00 = _LC3_A18;
-- Node name is 'h01'
-- Equation name is 'h01', type is output
h01 = _LC2_A18;
-- Node name is 'h02'
-- Equation name is 'h02', type is output
h02 = _LC5_A18;
-- Node name is 'h03'
-- Equation name is 'h03', type is output
h03 = _LC6_A18;
-- Node name is 'h04'
-- Equation name is 'h04', type is output
h04 = !_LC7_A18;
-- Node name is 'h05'
-- Equation name is 'h05', type is output
h05 = _LC1_A18;
-- Node name is 'h06'
-- Equation name is 'h06', type is output
h06 = _LC8_A18;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -