jsq60.vhd

这是一个数字时钟的Verilog程序 仿真通过 能实现秒 分 时 计时

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY jsq60 IS
   PORT(clk:IN STD_LOGIC;
        en0,en1,cin:IN STD_LOGIC;
        datain:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        co:OUT STD_LOGIC;
        q0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        q1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); 
END jsq60;
ARCHITECTURE rtl OF jsq60 IS
  SIGNAL s0n:STD_LOGIC_VECTOR(3 DOWNTO 0);
  SIGNAL s1n:STD_LOGIC_VECTOR(3 DOWNTO 0);
  BEGIN
   q0<=s0n;
   q1<=s1n;
   PROCESS(clk,en0)
    BEGIN
     IF(en0='1')THEN
       s0n<=datain;
     ELSIF(clk'EVENT AND clk='1')THEN
         IF(cin='1')THEN
           IF(s0n=9)THEN
              s0n<="0000";
           ELSE
              s0n<=s0n+1;
           END IF;
         END IF;
     END IF;
  END PROCESS;
  PROCESS(clk,en1)
   BEGIN
    IF(en1='1')THEN
       s1n<=datain;
    ELSIF(clk'EVENT AND clk='1')THEN
      IF(cin='1'AND s0n=9)THEN
         IF(s1n=5)THEN
            s1n<="0000";
         ELSE 
            s1n<=s1n+1;
         END IF;
      END IF;
   END IF;
  END PROCESS;
PROCESS(s0n,s1n,cin)
  BEGIN
    IF(cin='1' AND s0n=9 AND s1n=5)THEN
      co<='1';
    ELSE
      co<='0';
    END IF;
 END PROCESS;
END rtl;