clock24.vhd

这是一个数字时钟的Verilog程序 仿真通过 能实现秒 分 时 计时

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY WORK;
USE WORK.clock24coms.ALL;

ENTITY clock24 IS
  PORT(clk,en0,en1,en2,en3,en4,en5,cin:IN STD_LOGIC;
       datain:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       s0,s1,m0,m1,h0,h1:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
       co:OUT STD_LOGIC);
END clock24;

ARCHITECTURE rtl OF clock24 IS
SIGNAL u0_co,u1_co,u2_co:STD_LOGIC;
SIGNAL u0_q0,u0_q1,u1_q0,u1_q1,u2_q0,u2_q1:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
  u0:jsq60 PORT MAP(clk,en0,en1,cin,datain,u0_co,u0_q0,u0_q1);
  u1:jsq60 PORT MAP(clk,en2,en3,u0_co,datain,u1_co,u1_q0,u1_q1);
  u2:jsq24 PORT MAP(clk,en4,en5,u1_co,datain,u2_co,u2_q0,u2_q1);
  u3:decoder PORT MAP(u0_q0,s0);
  u4:decoder PORT MAP(u0_q1,s1);
  u5:decoder PORT MAP(u1_q0,m0);
  u6:decoder PORT MAP(u1_q1,m1);
  u7:decoder PORT MAP(u2_q0,h0);
  u8:decoder PORT MAP(u2_q1,h1);
  co<=u2_co;
END rtl;