📄 rt.rpt
字号:
Total input pins required: 12
Total input I/O cell registers required: 0
Total output pins required: 27
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 619
Total flipflops required: 391
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 62/1152 ( 5%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 8 8 8 8 8 7 5 8 8 8 8 8 6 7 7 8 7 8 8 8 8 8 7 8 182/8
B: 8 8 7 8 8 6 8 7 8 4 7 8 8 8 8 8 8 0 8 3 8 6 8 8 6 166/8
C: 0 8 8 8 0 0 8 8 1 8 8 8 8 0 0 0 0 7 0 0 0 0 6 8 0 86/8
D: 8 0 0 0 0 8 0 0 0 8 8 0 0 0 0 6 8 0 2 0 0 0 0 8 0 56/0
E: 8 6 8 1 8 8 2 1 0 8 0 8 8 8 0 0 6 0 0 0 0 0 8 0 0 80/8
F: 7 1 0 2 4 0 1 3 8 1 8 0 0 0 3 0 8 1 0 0 0 0 0 2 0 49/0
Total: 39 31 31 27 28 30 26 24 25 37 39 32 32 22 18 21 38 15 18 11 16 14 30 33 14 619/32
Device-Specific Information: k:\vhdl\n\n\t2t\rt.rpt
rt
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
126 - - - -- INPUT 0 0 0 2 A2048
54 - - - -- INPUT G 0 0 0 2 B2048
55 - - - -- INPUT G 0 0 0 3 C23
9 - - B -- INPUT 0 0 0 3 dataIn0
96 - - B -- INPUT 0 0 0 3 dataIn1
56 - - - -- INPUT 0 0 0 3 dataIn2
98 - - B -- INPUT 0 0 0 3 dataIn3
10 - - B -- INPUT 0 0 0 3 dataIn4
124 - - - -- INPUT 0 0 0 3 dataIn5
99 - - B -- INPUT 0 0 0 3 dataIn6
97 - - B -- INPUT 0 0 0 3 dataIn7
125 - - - -- INPUT G 0 0 0 0 M16
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: k:\vhdl\n\n\t2t\rt.rpt
rt
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
12 - - C -- OUTPUT 0 1 0 0 dataOut0
14 - - C -- OUTPUT 0 1 0 0 dataOut1
92 - - C -- OUTPUT 0 1 0 0 dataOut2
143 - - A -- OUTPUT 0 1 0 0 dataOut3
102 - - A -- OUTPUT 0 1 0 0 dataOut4
100 - - A -- OUTPUT 0 1 0 0 dataOut5
8 - - A -- OUTPUT 0 1 0 0 dataOut6
22 - - D -- OUTPUT 0 1 0 0 dataOut7
73 - - - 01 OUTPUT 0 1 0 0 data0
132 - - - 16 OUTPUT 0 1 0 0 data1
47 - - - 16 OUTPUT 0 1 0 0 data2
117 - - - 05 OUTPUT 0 1 0 0 data3
32 - - F -- OUTPUT 0 1 0 0 data4
7 - - A -- OUTPUT 0 1 0 0 data5
109 - - A -- OUTPUT 0 1 0 0 data6
144 - - A -- OUTPUT 0 1 0 0 data7
130 - - - 15 OUTPUT 0 1 0 0 RD
11 - - C -- OUTPUT 0 1 0 0 SLOT
27 - - E -- OUTPUT 0 1 0 0 usedw0
28 - - E -- OUTPUT 0 1 0 0 usedw1
29 - - E -- OUTPUT 0 1 0 0 usedw2
87 - - E -- OUTPUT 0 1 0 0 usedw3
26 - - E -- OUTPUT 0 1 0 0 usedw4
86 - - E -- OUTPUT 0 1 0 0 usedw5
83 - - E -- OUTPUT 0 1 0 0 usedw6
101 - - A -- OUTPUT 0 0 0 0 usedw7
44 - - - 18 OUTPUT 0 1 0 0 WR
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: k:\vhdl\n\n\t2t\rt.rpt
rt
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - C 23 OR2 ! 0 2 0 2 |R2R:1|LPM_ADD_SUB:378|addcore:adder|:59
- 1 - C 23 OR2 ! 0 3 0 2 |R2R:1|LPM_ADD_SUB:378|addcore:adder|:63
- 5 - E 13 DFFE 0 3 0 3 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|b_full
- 8 - E 13 DFFE 0 3 0 3 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|b_non_empty
- 2 - E 16 DFFE 0 3 1 4 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|dffs0
- 5 - E 16 DFFE 0 4 1 3 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|dffs1
- 7 - E 22 DFFE 0 4 1 4 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|dffs2
- 1 - E 22 DFFE 0 4 1 3 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|dffs3
- 4 - E 22 DFFE 0 4 1 4 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|dffs4
- 3 - E 22 DFFE 0 4 1 3 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|dffs5
- 6 - E 16 DFFE 0 4 1 2 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|dffs6
- 1 - E 16 OR2 0 3 0 3 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|lpm_add_sub:add_sub|addcore:adder|pcarry1
- 5 - E 22 OR2 0 3 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|lpm_add_sub:add_sub|addcore:adder|pcarry2
- 6 - E 22 OR2 0 4 0 3 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|lpm_add_sub:add_sub|addcore:adder|pcarry3
- 8 - E 22 OR2 0 3 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|lpm_add_sub:add_sub|addcore:adder|pcarry4
- 2 - E 22 OR2 0 4 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|lpm_add_sub:add_sub|addcore:adder|pcarry5
- 4 - E 16 OR2 s 0 4 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|~158~1
- 6 - E 13 OR2 s 0 4 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|~158~2
- 3 - E 16 AND2 s 0 4 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|~169~1
- 2 - E 13 AND2 s 0 4 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|~169~2
- 7 - E 13 OR2 s 0 4 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|~190~1
- 3 - E 13 OR2 s 0 4 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|~192~1
- 6 - A 05 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs0
- 8 - A 22 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs1
- 8 - A 19 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs2
- 8 - A 09 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs3
- 8 - A 21 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs4
- 7 - A 24 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs5
- 8 - A 02 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs6
- 8 - A 18 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs7
- 8 - A 05 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs0
- 7 - A 22 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs1
- 7 - A 19 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs2
- 7 - A 09 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs3
- 6 - A 21 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs4
- 6 - A 24 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs5
- 7 - A 02 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs6
- 7 - A 18 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs7
- 5 - A 05 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs0
- 6 - A 22 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs1
- 6 - A 19 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs2
- 6 - A 09 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs3
- 5 - A 21 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs4
- 5 - A 24 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs5
- 6 - A 02 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs6
- 6 - A 18 DFFE 0 5 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs7
- 4 - A 05 DFFE 0 3 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:137|dffs0
- 2 - A 15 DFFE 0 3 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:137|dffs1
- 8 - A 15 DFFE 0 3 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:137|dffs2
- 5 - A 15 DFFE 0 3 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:137|dffs3
- 3 - A 15 DFFE 0 3 0 1 |R2R:1|LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo⌨️ 快捷键说明
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