📄 rt.rpt
字号:
dataIn0 | 9 100 | dataOut5
dataIn4 | 10 99 | dataIn6
SLOT | 11 98 | dataIn3
dataOut0 | 12 97 | dataIn7
RESERVED | 13 96 | dataIn1
dataOut1 | 14 95 | RESERVED
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
RESERVED | 17 92 | dataOut2
RESERVED | 18 91 | RESERVED
RESERVED | 19 EPF10K20TC144-3 90 | RESERVED
RESERVED | 20 89 | RESERVED
RESERVED | 21 88 | RESERVED
dataOut7 | 22 87 | usedw3
RESERVED | 23 86 | usedw5
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
usedw4 | 26 83 | usedw6
usedw0 | 27 82 | RESERVED
usedw1 | 28 81 | RESERVED
usedw2 | 29 80 | RESERVED
RESERVED | 30 79 | RESERVED
RESERVED | 31 78 | RESERVED
data4 | 32 77 | ^MSEL0
RESERVED | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | data0
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R G R R R W V R d R R G R V V B C d G G R R V R R R R G R R R R V R
E E E N E E E R C E a E E N E C C 2 2 a N N E E C E E E E N E E E E C E
S S S D S S S C S t S S D S C C 0 3 t D D S S C S S S S D S S S S C S
E E E I E E E I E a E E I E I I 4 a I I E E I E E E E I E E E E I E
R R R O R R R O R 2 R R O R N N 8 I N N R R O R R R R O R R R R O R
V V V V V V V V V V T T n T T V V V V V V V V V V V
E E E E E E E E E E 2 E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: k:\vhdl\n\n\t2t\rt.rpt
rt
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 6/22( 27%)
A2 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 19/22( 86%)
A3 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 6/22( 27%)
A4 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 1/2 0/2 10/22( 45%)
A5 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
A6 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 6/22( 27%)
A7 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 2/2 0/2 9/22( 40%)
A8 5/ 8( 62%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
A9 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 19/22( 86%)
A10 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
A11 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
A12 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
A13 6/ 8( 75%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 9/22( 40%)
A14 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 2/2 0/2 9/22( 40%)
A15 7/ 8( 87%) 0/ 8( 0%) 7/ 8( 87%) 1/2 0/2 9/22( 40%)
A16 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 0/2 5/22( 22%)
A17 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 11/22( 50%)
A18 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 19/22( 86%)
A19 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 19/22( 86%)
A20 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 14/22( 63%)
A21 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 19/22( 86%)
A22 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 19/22( 86%)
A23 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 2/2 0/2 9/22( 40%)
A24 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 19/22( 86%)
B1 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 4/22( 18%)
B2 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 17/22( 77%)
B3 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
B4 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
B5 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 5/22( 22%)
B6 6/ 8( 75%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 9/22( 40%)
B7 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 12/22( 54%)
B8 7/ 8( 87%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 6/22( 27%)
B9 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 17/22( 77%)
B10 4/ 8( 50%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
B11 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
B12 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 9/22( 40%)
B13 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 17/22( 77%)
B14 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 11/22( 50%)
B15 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 19/22( 86%)
B16 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 17/22( 77%)
B18 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 17/22( 77%)
B19 3/ 8( 37%) 3/ 8( 37%) 0/ 8( 0%) 1/2 0/2 9/22( 40%)
B20 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 17/22( 77%)
B21 6/ 8( 75%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 9/22( 40%)
B22 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 17/22( 77%)
B23 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 8/22( 36%)
B24 6/ 8( 75%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 9/22( 40%)
C2 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
C3 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
C4 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 6/22( 27%)
C7 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 1/2 0/2 12/22( 54%)
C8 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 6/22( 27%)
C9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 4/22( 18%)
C10 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
C11 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 9/22( 40%)
C12 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 1/2 0/2 11/22( 50%)
C17 7/ 8( 87%) 2/ 8( 25%) 5/ 8( 62%) 1/2 0/2 5/22( 22%)
C22 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 2/2 0/2 4/22( 18%)
C23 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 6/22( 27%)
D1 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 0/2 6/22( 27%)
D6 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 1/2 0/2 5/22( 22%)
D10 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
D11 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
D15 6/ 8( 75%) 3/ 8( 37%) 0/ 8( 0%) 2/2 0/2 4/22( 18%)
D16 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 8/22( 36%)
D18 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 2/2 0/2 2/22( 9%)
D23 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 8/22( 36%)
E1 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 9/22( 40%)
E2 6/ 8( 75%) 3/ 8( 37%) 1/ 8( 12%) 1/2 0/2 9/22( 40%)
E3 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
E4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 3/22( 13%)
E5 8/ 8(100%) 1/ 8( 12%) 8/ 8(100%) 1/2 0/2 4/22( 18%)
E6 8/ 8(100%) 5/ 8( 62%) 2/ 8( 25%) 2/2 0/2 8/22( 36%)
E7 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
E8 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
E10 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
E12 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 9/22( 40%)
E13 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 9/22( 40%)
E16 6/ 8( 75%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 7/22( 31%)
E22 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 4/22( 18%)
F1 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
F2 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
F4 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
F5 4/ 8( 50%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
F7 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
F8 3/ 8( 37%) 3/ 8( 37%) 1/ 8( 12%) 1/2 0/2 4/22( 18%)
F9 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 4/22( 18%)
F10 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
F11 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 11/22( 50%)
F14 3/ 8( 37%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 3/22( 13%)
F16 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
F17 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
F23 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
A25 8/8 (100%) 2/8 ( 25%) 6/8 ( 75%) 1/2 2/2 16/22( 72%)
B25 8/8 (100%) 0/8 ( 0%) 8/8 (100%) 1/2 2/2 16/22( 72%)
C25 8/8 (100%) 8/8 (100%) 2/8 ( 25%) 1/2 2/2 16/22( 72%)
E25 8/8 (100%) 6/8 ( 75%) 2/8 ( 25%) 1/2 2/2 16/22( 72%)
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 33/96 ( 34%)
Total logic cells used: 619/1152 ( 53%)
Total embedded cells used: 32/48 ( 66%)
Total EABs used: 4/6 ( 66%)
Average fan-in: 3.19/4 ( 79%)
Total fan-in: 1979/4608 ( 42%)
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