t2t.fit.summary

用VHDL实现的通信滑码处理

Fitter Status : Successful - Fri May 25 11:01:41 2007
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Web Edition
Revision Name : T2T
Top-level Entity Name : T2T
Family : Stratix
Device : EP1S10F484C5
Timing Models : Final
Total logic elements : 58 / 10,570 ( < 1 % )
Total pins : 10 / 336 ( 3 % )
Total virtual pins : 0
Total memory bits : 128 / 920,448 ( < 1 % )
DSP block 9-bit elements : 0 / 48 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )