📄 t2t.rpt
字号:
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 7 8 7 6 8 2 8 7 8 1 7 6 8 2 8 8 4 8 8 2 8 8 8 8 8 155/8
B: 0 0 0 8 0 0 8 5 0 0 0 0 0 0 0 0 0 8 6 8 0 8 0 8 0 59/0
C: 8 1 8 3 8 0 0 8 8 8 8 8 8 8 2 0 8 0 0 0 8 0 0 0 8 102/8
Total: 15 9 15 17 16 2 16 20 16 9 15 14 16 10 10 8 12 16 14 10 16 16 8 16 16 316/16
Device-Specific Information: k:\vhdl\n\n\t2t\t2t.rpt
t2t
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
42 - - - -- INPUT 0 0 0 2 C2
43 - - - -- INPUT G 0 0 0 2 C3
1 - - - -- INPUT G 0 0 0 0 C8
2 - - - -- INPUT 0 0 0 3 data0
44 - - - -- INPUT 0 0 0 3 data1
84 - - - -- INPUT 0 0 0 3 data2
18 - - A -- INPUT 0 0 0 3 data3
69 - - A -- INPUT 0 0 0 3 data4
71 - - A -- INPUT 0 0 0 3 data5
73 - - A -- INPUT 0 0 0 3 data6
17 - - A -- INPUT 0 0 0 3 data7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: k:\vhdl\n\n\t2t\t2t.rpt
t2t
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
70 - - A -- OUTPUT 0 1 0 0 COUT
66 - - B -- OUTPUT 0 1 0 0 dataout0
65 - - B -- OUTPUT 0 1 0 0 dataout1
21 - - B -- OUTPUT 0 1 0 0 dataout2
64 - - B -- OUTPUT 0 1 0 0 dataout3
24 - - B -- OUTPUT 0 1 0 0 dataout4
67 - - B -- OUTPUT 0 1 0 0 dataout5
23 - - B -- OUTPUT 0 1 0 0 dataout6
22 - - B -- OUTPUT 0 1 0 0 dataout7
47 - - - 14 OUTPUT 0 1 0 0 q0
54 - - - 21 OUTPUT 0 1 0 0 q1
50 - - - 17 OUTPUT 0 1 0 0 q2
78 - - - 24 OUTPUT 0 1 0 0 q3
81 - - - 22 OUTPUT 0 1 0 0 q4
83 - - - 13 OUTPUT 0 1 0 0 q5
80 - - - 23 OUTPUT 0 1 0 0 q6
51 - - - 18 OUTPUT 0 1 0 0 q7
61 - - C -- OUTPUT 0 1 0 0 RD
25 - - B -- OUTPUT 0 1 0 0 slot
60 - - C -- OUTPUT 0 1 0 0 WR
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: k:\vhdl\n\n\t2t\t2t.rpt
t2t
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - B 21 AND2 0 2 0 2 |LPM_ADD_SUB:490|addcore:adder|:59
- 6 - B 21 AND2 0 3 0 2 |LPM_ADD_SUB:490|addcore:adder|:63
- 3 - A 03 DFFE 0 4 0 3 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|b_full
- 6 - A 03 DFFE 0 4 0 3 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|b_non_empty
- 1 - A 03 DFFE 0 3 0 3 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|dffs0
- 1 - A 07 DFFE 0 4 0 3 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|dffs1
- 5 - A 07 DFFE 0 4 0 4 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|dffs2
- 7 - A 07 DFFE 0 4 0 3 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|dffs3
- 7 - A 09 DFFE 0 4 0 3 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|dffs4
- 6 - A 09 DFFE 0 4 0 3 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|dffs5
- 3 - A 09 DFFE 0 4 0 2 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|dffs6
- 4 - A 07 OR2 0 3 0 3 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|lpm_add_sub:add_sub|addcore:adder|pcarry1
- 6 - A 07 OR2 0 3 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|lpm_add_sub:add_sub|addcore:adder|pcarry2
- 3 - A 07 OR2 0 4 0 2 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|lpm_add_sub:add_sub|addcore:adder|pcarry3
- 1 - A 09 OR2 0 3 0 2 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|lpm_add_sub:add_sub|addcore:adder|pcarry4
- 2 - A 09 OR2 0 3 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|lpm_add_sub:add_sub|addcore:adder|pcarry5
- 7 - A 03 AND2 0 2 0 15 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|valid_rreq
- 2 - A 03 AND2 s ! 0 3 0 2 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|~158~1
- 2 - A 07 OR2 s 0 3 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|~158~2
- 5 - A 03 OR2 s 0 4 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|~158~3
- 8 - A 07 AND2 s 0 3 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|~169~1
- 8 - A 09 AND2 s 0 3 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|~169~2
- 5 - A 09 AND2 s 0 4 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|~169~3
- 8 - A 15 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs0
- 8 - A 21 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs1
- 8 - A 17 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs2
- 8 - A 24 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs3
- 8 - A 22 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs4
- 3 - A 14 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs5
- 8 - A 23 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs6
- 8 - A 18 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs7
- 7 - A 15 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs0
- 7 - A 21 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs1
- 7 - A 17 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs2
- 7 - A 24 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs3
- 7 - A 22 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs4
- 8 - A 14 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs5
- 7 - A 23 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs6
- 6 - A 18 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs7
- 6 - A 15 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs0
- 6 - A 21 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs1
- 6 - A 17 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs2
- 6 - A 24 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs3
- 6 - A 22 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs4
- 7 - A 14 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs5
- 6 - A 23 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs6
- 5 - A 18 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs7
- 5 - A 15 DFFE 0 3 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:137|dffs0
- 6 - A 06 DFFE 0 3 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:137|dffs1
- 3 - A 16 DFFE 0 3 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:137|dffs2
- 1 - A 16 DFFE 0 3 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:137|dffs3
- 8 - A 06 DFFE 0 3 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:137|dffs4
- 6 - A 14 DFFE 0 3 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:137|dffs5
- 5 - A 16 DFFE 0 3 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:137|dffs6
- 7 - A 16 DFFE 0 3 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:137|dffs7
- 5 - A 20 DFFE 0 5 0 12 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:163|dffs0
- 8 - A 20 DFFE 0 5 0 11 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:163|dffs1
- 7 - A 20 DFFE 0 4 0 4 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|pipefull0
- 7 - C 24 DFFE 0 5 0 11 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|pipefull3
- 6 - C 24 OR2 0 2 0 10 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|:220
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