📄 t2t.rpt
字号:
S S S S S S S V S G S F
E E E E E E E C E d d N E _ ^
R R R R R R R C R a a D R # D n
V V V V V V V I V t t I V T O C
E E E E E E E N E a C a q N q q E q C N E
D D D D D D D T D 0 8 2 5 T 4 6 D 3 K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | data6
^nCE | 14 72 | RESERVED
#TDI | 15 71 | data5
RESERVED | 16 70 | COUT
data7 | 17 69 | data4
data3 | 18 68 | GNDINT
RESERVED | 19 67 | dataout5
VCCINT | 20 66 | dataout0
dataout2 | 21 65 | dataout1
dataout7 | 22 EPF10K10LC84-3 64 | dataout3
dataout6 | 23 63 | VCCINT
dataout4 | 24 62 | RESERVED
slot | 25 61 | RD
GNDINT | 26 60 | WR
RESERVED | 27 59 | RESERVED
RESERVED | 28 58 | RESERVED
RESERVED | 29 57 | #TMS
RESERVED | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | q1
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ R R R R R V G C C d V G q R R q q R R
C n E E E E E C N 2 3 a C N 0 E E 2 7 E E
C C S S S S S C D t C D S S S S
I O E E E E E I I a I I E E E E
N N R R R R R N N 1 N N R R R R
T F V V V V V T T T T V V V V
I E E E E E E E E E
G D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: k:\vhdl\n\n\t2t\t2t.rpt
t2t
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 7/ 8( 87%) 2/ 8( 25%) 6/ 8( 75%) 1/2 0/2 9/22( 40%)
A2 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 9/22( 40%)
A3 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 7/22( 31%)
A4 6/ 8( 75%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 9/22( 40%)
A5 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
A6 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
A7 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 5/22( 22%)
A8 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
A9 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 7/22( 31%)
A10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
A11 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 9/22( 40%)
A12 6/ 8( 75%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 9/22( 40%)
A13 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 7/22( 31%)
A14 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 17/22( 77%)
A15 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 17/22( 77%)
A16 4/ 8( 50%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
A17 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 19/22( 86%)
A18 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 19/22( 86%)
A19 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 3/22( 13%)
A20 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
A21 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 19/22( 86%)
A22 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 19/22( 86%)
A23 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 19/22( 86%)
A24 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 19/22( 86%)
B4 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 0/2 7/22( 31%)
B7 8/ 8(100%) 4/ 8( 50%) 5/ 8( 62%) 1/2 0/2 5/22( 22%)
B8 5/ 8( 62%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
B17 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 0/2 6/22( 27%)
B18 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 2/2 0/2 6/22( 27%)
B19 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 0/2 7/22( 31%)
B21 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
B23 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 0/2 7/22( 31%)
C1 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 6/22( 27%)
C2 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
C3 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 13/22( 59%)
C4 3/ 8( 37%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
C5 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 1/2 0/2 7/22( 31%)
C8 8/ 8(100%) 1/ 8( 12%) 7/ 8( 87%) 1/2 0/2 4/22( 18%)
C9 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 8/22( 36%)
C10 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
C11 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 9/22( 40%)
C12 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
C13 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 12/22( 54%)
C14 2/ 8( 25%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 3/22( 13%)
C16 8/ 8(100%) 5/ 8( 62%) 2/ 8( 25%) 1/2 0/2 7/22( 31%)
C20 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 1/2 0/2 5/22( 22%)
C24 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 1/2 0/2 10/22( 45%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
A25 8/8 (100%) 0/8 ( 0%) 8/8 (100%) 1/2 2/2 16/22( 72%)
C25 8/8 (100%) 8/8 (100%) 1/8 ( 12%) 1/2 2/2 16/22( 72%)
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 25/53 ( 47%)
Total logic cells used: 316/576 ( 54%)
Total embedded cells used: 16/24 ( 66%)
Total EABs used: 2/3 ( 66%)
Average fan-in: 3.20/4 ( 80%)
Total fan-in: 1012/2304 ( 43%)
Total input pins required: 11
Total input I/O cell registers required: 0
Total output pins required: 20
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 316
Total flipflops required: 200
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 34/ 576 ( 5%)
Logic Cell and Embedded Cell Counts
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -