📄 t2t.sim.rpt
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The following table displays output ports that do not toggle to 1 during simulation.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|dpram_17k:FIFOram|altsyncram_sga1:altsyncram1|q_b[0] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|dpram_17k:FIFOram|altsyncram_sga1:altsyncram1|q_b[0] ; portbdataout0 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[1] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[1] ; regout ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[1] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella1~COUT ; cout0 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[1] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella1~COUTCOUT1_2 ; cout1 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[2] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[2] ; regout ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[2] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella2~COUT ; cout0 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[2] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella2~COUTCOUT1 ; cout1 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[3] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[3] ; regout ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[3] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella3~COUT ; cout ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[4] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[4] ; regout ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[4] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella4~COUT ; cout0 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[4] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella4~COUTCOUT1_2 ; cout1 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[5] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[5] ; regout ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[5] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella5~COUT ; cout0 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[5] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella5~COUTCOUT1_2 ; cout1 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[6] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[6] ; regout ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[0] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[0] ; regout ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[0] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella0~COUT ; cout0 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[0] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella0~COUTCOUT1_3 ; cout1 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[1] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[1] ; regout ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[1] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella1~COUT ; cout0 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[1] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella1~COUTCOUT1_2 ; cout1 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[2] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[2] ; regout ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[2] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella2~COUT ; cout0 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[2] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella2~COUTCOUT1 ; cout1 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[3] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[3] ; regout ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[3] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella3~COUT ; cout ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[4] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[4] ; regout ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[4] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella4~COUT ; cout0 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[4] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella4~COUTCOUT1_2 ; cout1 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[5] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[5] ; regout ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[5] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella5~COUT ; cout0 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[5] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella5~COUTCOUT1_2 ; cout1 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[6] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[6] ; regout ;
; |T2T|startSend ; |T2T|startSend ; regout ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|cntr_cd7:count_usedw|safe_q[5] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|cntr_cd7:count_usedw|counter_cella5~COUTCOUT1_9 ; cout1 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|cntr_cd7:count_usedw|safe_q[4] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|cntr_cd7:count_usedw|counter_cella4~COUTCOUT1_9 ; cout1 ;
; |T2T|rtl~26 ; |T2T|rtl~26 ; combout ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|b_full~85 ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|b_full~85 ; combout ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|b_full~86 ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|b_full~86 ; combout ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|b_full~87 ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|b_full~87 ; combout ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|b_non_empty~77 ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|b_non_empty~77 ; combout ;
; |T2T|cnt[2] ; |T2T|cnt[2] ; regout ;
; |T2T|cnt[1] ; |T2T|cnt[1] ; regout ;
; |T2T|cnt[0] ; |T2T|cnt[0] ; regout ;
; |T2T|startSend~213 ; |T2T|startSend~213 ; combout ;
; |T2T|add~112 ; |T2T|add~112 ; combout ;
; |T2T|cnt[3]~79 ; |T2T|cnt[3]~79 ; combout ;
; |T2T|q[0] ; |T2T|q[0] ; padio ;
+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|dpram_17k:FIFOram|altsyncram_sga1:altsyncram1|q_b[0] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|dpram_17k:FIFOram|altsyncram_sga1:altsyncram1|q_b[0] ; portbdataout0 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[0] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[0] ; regout ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[0] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella0~COUT ; cout0 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[0] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella0~COUTCOUT1_3 ; cout1 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[1] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[1] ; regout ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[1] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella1~COUT ; cout0 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[1] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella1~COUTCOUT1_2 ; cout1 ;
; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[2] ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[2] ; regout ;
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