t2t.map.rpt

用VHDL实现的通信滑码处理

; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 40    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 11    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 6:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; Yes        ; |T2T|sts[1]                ;
; 6:1                ; 4 bits    ; 16 LEs        ; 4 LEs                ; 12 LEs                 ; Yes        ; |T2T|cnt[3]                ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for LPM_FIFO:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|dpram_17k:FIFOram|altsyncram_sga1:altsyncram1 ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------+
; Assignment                      ; Value              ; from ; to                                                                             ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                              ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------+


+----------------------------------------------------------+
; Parameter Settings for User Entity Instance: LPM_FIFO:U1 ;
+-------------------------+-------+------------------------+
; Parameter Name          ; Value ; Type                   ;
+-------------------------+-------+------------------------+
; lpm_width               ; 1     ; Integer                ;
; LPM_NUMWORDS            ; 128   ; Integer                ;
; LPM_WIDTHU              ; 7     ; Integer                ;
; LPM_SHOWAHEAD           ; OFF   ; Untyped                ;
; UNDERFLOW_CHECKING      ; ON    ; Untyped                ;
; OVERFLOW_CHECKING       ; ON    ; Untyped                ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF   ; Untyped                ;
; USE_EAB                 ; ON    ; Untyped                ;
+-------------------------+-------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in G:/N/T2T/T2T.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
    Info: Processing started: Fri May 25 11:00:50 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off T2T -c T2T
Warning: Using design file T2T.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: T2T-a
    Info: Found entity 1: T2T
Warning: Found the following files while searching for definition of entity "T2T", but did not use these files because already using a different file containing the entity definition
    Warning: File: T2T.bdf
Info: Elaborating entity "T2T" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at T2T.vhd(39): object "full" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at T2T.vhd(39): object "empty" assigned a value but never read
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/LPM_FIFO.tdf
    Info: Found entity 1: lpm_fifo
Info: Elaborating entity "LPM_FIFO" for hierarchy "LPM_FIFO:U1"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/scfifo.tdf
    Info: Found entity 1: scfifo
Info: Elaborating entity "scfifo" for hierarchy "LPM_FIFO:U1|scfifo:myFIFO"
Info: Found 1 design units, including 1 entities, in source file db/scfifo_sin.tdf
    Info: Found entity 1: scfifo_sin
Info: Elaborating entity "scfifo_sin" for hierarchy "LPM_FIFO:U1|scfifo:myFIFO|scfifo_sin:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_pek.tdf
    Info: Found entity 1: a_dpfifo_pek
Info: Elaborating entity "a_dpfifo_pek" for hierarchy "LPM_FIFO:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo"
Info: Found 1 design units, including 1 entities, in source file db/a_fefifo_t7f.tdf
    Info: Found entity 1: a_fefifo_t7f
Info: Elaborating entity "a_fefifo_t7f" for hierarchy "LPM_FIFO:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state"
Info: Found 1 design units, including 1 entities, in source file db/cntr_cd7.tdf
    Info: Found entity 1: cntr_cd7
Info: Elaborating entity "cntr_cd7" for hierarchy "LPM_FIFO:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|cntr_cd7:count_usedw"
Info: Found 1 design units, including 1 entities, in source file db/dpram_17k.tdf
    Info: Found entity 1: dpram_17k
Info: Elaborating entity "dpram_17k" for hierarchy "LPM_FIFO:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|dpram_17k:FIFOram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_sga1.tdf
    Info: Found entity 1: altsyncram_sga1
Info: Elaborating entity "altsyncram_sga1" for hierarchy "LPM_FIFO:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|dpram_17k:FIFOram|altsyncram_sga1:altsyncram1"
Info: Found 1 design units, including 1 entities, in source file db/cntr_ue8.tdf
    Info: Found entity 1: cntr_ue8
Info: Elaborating entity "cntr_ue8" for hierarchy "LPM_FIFO:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count"
Info: Implemented 69 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 6 output pins
    Info: Implemented 58 logic cells
    Info: Implemented 1 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
    Info: Processing ended: Fri May 25 11:01:09 2007
    Info: Elapsed time: 00:00:20