📄 t2t.map.rpt
字号:
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Maximum Number of M512 Memory Blocks ; -1 ; -1 ;
; Maximum Number of M4K Memory Blocks ; -1 ; -1 ;
; Maximum Number of M-RAM Memory Blocks ; -1 ; -1 ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
+--------------------------------------------------------------------+--------------------+--------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------+-----------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------+-----------------------------------------------------------+
; T2T.vhd ; yes ; Other ; G:/N/T2T/T2T.vhd ;
; LPM_FIFO.tdf ; yes ; Megafunction ; c:/altera/quartus51/libraries/megafunctions/LPM_FIFO.tdf ;
; scfifo.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/scfifo.inc ;
; scfifo.tdf ; yes ; Megafunction ; c:/altera/quartus51/libraries/megafunctions/scfifo.tdf ;
; a_regfifo.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/a_regfifo.inc ;
; a_dpfifo.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/a_dpfifo.inc ;
; a_i2fifo.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/a_i2fifo.inc ;
; a_fffifo.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/a_fffifo.inc ;
; a_f2fifo.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/a_f2fifo.inc ;
; aglobal51.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/aglobal51.inc ;
; db/scfifo_sin.tdf ; yes ; Auto-Generated Megafunction ; G:/N/T2T/db/scfifo_sin.tdf ;
; db/a_dpfifo_pek.tdf ; yes ; Auto-Generated Megafunction ; G:/N/T2T/db/a_dpfifo_pek.tdf ;
; db/a_fefifo_t7f.tdf ; yes ; Auto-Generated Megafunction ; G:/N/T2T/db/a_fefifo_t7f.tdf ;
; db/cntr_cd7.tdf ; yes ; Auto-Generated Megafunction ; G:/N/T2T/db/cntr_cd7.tdf ;
; db/dpram_17k.tdf ; yes ; Auto-Generated Megafunction ; G:/N/T2T/db/dpram_17k.tdf ;
; db/altsyncram_sga1.tdf ; yes ; Auto-Generated Megafunction ; G:/N/T2T/db/altsyncram_sga1.tdf ;
; db/cntr_ue8.tdf ; yes ; Auto-Generated Megafunction ; G:/N/T2T/db/cntr_ue8.tdf ;
+----------------------------------+-----------------+------------------------------+-----------------------------------------------------------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Total logic elements ; 58 ;
; -- Combinational with no register ; 18 ;
; -- Register only ; 2 ;
; -- Combinational with a register ; 38 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 20 ;
; -- 3 input functions ; 26 ;
; -- 2 input functions ; 10 ;
; -- 1 input functions ; 0 ;
; -- 0 input functions ; 0 ;
; -- Combinational cells for routing ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 40 ;
; -- arithmetic mode ; 18 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 40 ;
; Total logic cells in carry chains ; 21 ;
; I/O pins ; 10 ;
; Total memory bits ; 128 ;
; Maximum fan-out node ; clock ;
; Maximum fan-out ; 26 ;
; Total fan-out ; 255 ;
; Average fan-out ; 3.70 ;
+---------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+-------------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------------------------------------------------------------------+
; |T2T ; 58 (27) ; 40 ; 128 ; 0 ; 0 ; 0 ; 0 ; 10 ; 0 ; 18 (10) ; 2 (2) ; 38 (15) ; 21 (0) ; 0 (0) ; |T2T ;
; |lpm_fifo:U1| ; 31 (0) ; 23 ; 128 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 0 (0) ; 23 (0) ; 21 (0) ; 0 (0) ; |T2T|lpm_fifo:U1 ;
; |scfifo:myFIFO| ; 31 (0) ; 23 ; 128 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 0 (0) ; 23 (0) ; 21 (0) ; 0 (0) ; |T2T|lpm_fifo:U1|scfifo:myFIFO ;
; |scfifo_sin:auto_generated| ; 31 (0) ; 23 ; 128 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 0 (0) ; 23 (0) ; 21 (0) ; 0 (0) ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated ;
; |a_dpfifo_pek:dpfifo| ; 31 (2) ; 23 ; 128 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (2) ; 0 (0) ; 23 (0) ; 21 (0) ; 0 (0) ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo ;
; |a_fefifo_t7f:fifo_state| ; 15 (8) ; 9 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 9 (2) ; 7 (0) ; 0 (0) ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state ;
; |cntr_cd7:count_usedw| ; 7 (7) ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (7) ; 7 (7) ; 0 (0) ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|cntr_cd7:count_usedw ;
; |cntr_ue8:rd_ptr_count| ; 7 (7) ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (7) ; 7 (7) ; 0 (0) ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count ;
; |cntr_ue8:wr_ptr| ; 7 (7) ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (7) ; 7 (7) ; 0 (0) ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr ;
; |dpram_17k:FIFOram| ; 0 (0) ; 0 ; 128 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|dpram_17k:FIFOram ;
; |altsyncram_sga1:altsyncram1| ; 0 (0) ; 0 ; 128 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |T2T|lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|dpram_17k:FIFOram|altsyncram_sga1:altsyncram1 ;
+-------------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+----------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+----------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|dpram_17k:FIFOram|altsyncram_sga1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 128 ; 1 ; 128 ; 1 ; 128 ; None ;
+----------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -