t2t.fit.eqn

用VHDL实现的通信滑码处理

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--A1L27Q is dataout[0]~reg0 at LC_X23_Y5_N9
--operation mode is normal

A1L27Q_lut_out = A1L26 & (write & (A1L27Q) # !write & A1L25) # !A1L26 & (A1L27Q);
A1L27Q = DFFEAS(A1L27Q_lut_out, GLOBAL(C8), VCC, , , , , , );


--K1_q_b[0] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|dpram_17k:FIFOram|altsyncram_sga1:altsyncram1|q_b[0] at M512_X20_Y5
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 1, Port B Logical Depth: 128, Port B Logical Width: 1
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
K1_q_b[0]_PORT_A_data_in = data[0];
K1_q_b[0]_PORT_A_data_in_reg = DFFE(K1_q_b[0]_PORT_A_data_in, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_A_address = BUS(H2_safe_q[0], H2_safe_q[1], H2_safe_q[2], H2_safe_q[3], H2_safe_q[4], H2_safe_q[5], H2_safe_q[6]);
K1_q_b[0]_PORT_A_address_reg = DFFE(K1_q_b[0]_PORT_A_address, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_address = BUS(H1_safe_q[0], H1_safe_q[1], H1_safe_q[2], H1_safe_q[3], H1_safe_q[4], H1_safe_q[5], H1_safe_q[6]);
K1_q_b[0]_PORT_B_address_reg = DFFE(K1_q_b[0]_PORT_B_address, K1_q_b[0]_clock_1, , , K1_q_b[0]_clock_enable_1);
K1_q_b[0]_PORT_A_write_enable = VCC;
K1_q_b[0]_PORT_A_write_enable_reg = DFFE(K1_q_b[0]_PORT_A_write_enable, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_read_enable = VCC;
K1_q_b[0]_PORT_B_read_enable_reg = DFFE(K1_q_b[0]_PORT_B_read_enable, K1_q_b[0]_clock_1, , , K1_q_b[0]_clock_enable_1);
K1_q_b[0]_clock_0 = GLOBAL(clock);
K1_q_b[0]_clock_1 = GLOBAL(clock);
K1_q_b[0]_clock_enable_0 = E1_valid_wreq;
K1_q_b[0]_clock_enable_1 = E1_valid_rreq;
K1_q_b[0]_PORT_B_data_out = MEMORY(K1_q_b[0]_PORT_A_data_in_reg, , K1_q_b[0]_PORT_A_address_reg, K1_q_b[0]_PORT_B_address_reg, K1_q_b[0]_PORT_A_write_enable_reg, K1_q_b[0]_PORT_B_read_enable_reg, , , K1_q_b[0]_clock_0, K1_q_b[0]_clock_1, K1_q_b[0]_clock_enable_0, K1_q_b[0]_clock_enable_1, , );
K1_q_b[0] = K1_q_b[0]_PORT_B_data_out[0];


--clock is clock at LC_X17_Y12_N4
--operation mode is normal

clock_lut_out = clock & (sts[0] # !sts[1]) # !clock & (!sts[1] & sts[0]);
clock = DFFEAS(clock_lut_out, GLOBAL(C8), VCC, , , , , , );


--read is read at LC_X21_Y6_N0
--operation mode is normal

read_lut_out = sts[0] & (sts[1] & A1L21 # !sts[1] & (read)) # !sts[0] & (read # !sts[1] & A1L21);
read = DFFEAS(read_lut_out, GLOBAL(C8), VCC, , , , , , );


--write is write at LC_X21_Y6_N7
--operation mode is normal

write_lut_out = write & (!sts[0] # !sts[1]) # !write & !sts[1] & c2flag & !sts[0];
write = DFFEAS(write_lut_out, GLOBAL(C8), VCC, , , , , , );


--sloti is sloti at LC_X23_Y5_N7
--operation mode is normal

sloti_lut_out = A1L41 & (sloti # sts[1] $ !sts[0]) # !A1L41 & sloti & (!sts[0] # !sts[1]);
sloti = DFFEAS(sloti_lut_out, GLOBAL(C8), VCC, , , , , , );


--datai[0] is datai[0] at LC_X24_Y5_N7
--operation mode is normal

datai[0]_lut_out = A1L22 & (startSend & datai[0] # !startSend & (A1L32)) # !A1L22 & (datai[0]);
datai[0] = DFFEAS(datai[0]_lut_out, GLOBAL(C8), VCC, , , , , , );


--A1L25 is dataout[0]~178 at LC_X23_Y5_N5
--operation mode is normal

A1L25 = sloti & datai[0] # !sloti & (K1_q_b[0]);


--sts[1] is sts[1] at LC_X23_Y5_N0
--operation mode is normal

sts[1]_lut_out = A1L41 # sts[1] $ (sts[0]);
sts[1] = DFFEAS(sts[1]_lut_out, GLOBAL(C8), VCC, , , , , , );


--sts[0] is sts[0] at LC_X24_Y5_N3
--operation mode is normal

sts[0]_lut_out = !sts[0] & (c3flag & startSend # !A1L39);
sts[0] = DFFEAS(sts[0]_lut_out, GLOBAL(C8), VCC, , , , , , );


--A1L26 is dataout[0]~179 at LC_X23_Y5_N8
--operation mode is normal

A1L26 = sts[1] & (sts[0]);


--F1_b_full is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|b_full at LC_X21_Y6_N6
--operation mode is normal

F1_b_full_lut_out = F1L5 & (F1L3 # F1_b_full & !read) # !F1L5 & F1_b_full & (!read);
F1_b_full = DFFEAS(F1_b_full_lut_out, GLOBAL(clock), VCC, , , , , , );


--E1_valid_wreq is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|valid_wreq at LC_X21_Y6_N2
--operation mode is normal

E1_valid_wreq = write & !F1_b_full;


--F1_b_non_empty is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|b_non_empty at LC_X21_Y6_N9
--operation mode is normal

F1_b_non_empty_lut_out = F1_b_full # write # F1L8 & F1_b_non_empty;
F1_b_non_empty = DFFEAS(F1_b_non_empty_lut_out, GLOBAL(clock), VCC, , , , , , );


--E1_valid_rreq is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|valid_rreq at LC_X21_Y6_N5
--operation mode is normal

E1_valid_rreq = F1_b_non_empty & (read);


--H2_safe_q[0] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[0] at LC_X22_Y5_N1
--operation mode is arithmetic

H2_safe_q[0]_lut_out = H2_safe_q[0] $ E1_valid_wreq;
H2_safe_q[0] = DFFEAS(H2_safe_q[0]_lut_out, GLOBAL(clock), VCC, , , , , , );

--H2L2 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella0~COUT at LC_X22_Y5_N1
--operation mode is arithmetic

H2L2_cout_0 = H2_safe_q[0];
H2L2 = CARRY(H2L2_cout_0);

--H2L3 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella0~COUTCOUT1_3 at LC_X22_Y5_N1
--operation mode is arithmetic

H2L3_cout_1 = H2_safe_q[0];
H2L3 = CARRY(H2L3_cout_1);


--H2_safe_q[1] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[1] at LC_X22_Y5_N2
--operation mode is arithmetic

H2_safe_q[1]_lut_out = H2_safe_q[1] $ (E1_valid_wreq & H2L2);
H2_safe_q[1] = DFFEAS(H2_safe_q[1]_lut_out, GLOBAL(clock), VCC, , , , , , );

--H2L5 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella1~COUT at LC_X22_Y5_N2
--operation mode is arithmetic

H2L5_cout_0 = !H2L2 # !H2_safe_q[1];
H2L5 = CARRY(H2L5_cout_0);

--H2L6 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella1~COUTCOUT1_2 at LC_X22_Y5_N2
--operation mode is arithmetic

H2L6_cout_1 = !H2L3 # !H2_safe_q[1];
H2L6 = CARRY(H2L6_cout_1);


--H2_safe_q[2] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[2] at LC_X22_Y5_N3
--operation mode is arithmetic

H2_safe_q[2]_lut_out = H2_safe_q[2] $ (E1_valid_wreq & !H2L5);
H2_safe_q[2] = DFFEAS(H2_safe_q[2]_lut_out, GLOBAL(clock), VCC, , , , , , );

--H2L8 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella2~COUT at LC_X22_Y5_N3
--operation mode is arithmetic

H2L8_cout_0 = H2_safe_q[2] & (!H2L5);
H2L8 = CARRY(H2L8_cout_0);

--H2L9 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella2~COUTCOUT1 at LC_X22_Y5_N3
--operation mode is arithmetic

H2L9_cout_1 = H2_safe_q[2] & (!H2L6);
H2L9 = CARRY(H2L9_cout_1);


--H2_safe_q[3] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[3] at LC_X22_Y5_N4
--operation mode is arithmetic

H2_safe_q[3]_lut_out = H2_safe_q[3] $ (E1_valid_wreq & H2L8);
H2_safe_q[3] = DFFEAS(H2_safe_q[3]_lut_out, GLOBAL(clock), VCC, , , , , , );

--H2L11 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella3~COUT at LC_X22_Y5_N4
--operation mode is arithmetic

H2L11 = H2L12;


--H2_safe_q[4] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[4] at LC_X22_Y5_N5
--operation mode is arithmetic

H2_safe_q[4]_carry_eqn = (!H2L11 & GND) # (H2L11 & VCC);
H2_safe_q[4]_lut_out = H2_safe_q[4] $ (E1_valid_wreq & !H2_safe_q[4]_carry_eqn);
H2_safe_q[4] = DFFEAS(H2_safe_q[4]_lut_out, GLOBAL(clock), VCC, , , , , , );

--H2L15 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella4~COUT at LC_X22_Y5_N5
--operation mode is arithmetic

H2L15_cout_0 = H2_safe_q[4] & (!H2L11);
H2L15 = CARRY(H2L15_cout_0);

--H2L16 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella4~COUTCOUT1_2 at LC_X22_Y5_N5
--operation mode is arithmetic

H2L16_cout_1 = H2_safe_q[4] & (!H2L11);
H2L16 = CARRY(H2L16_cout_1);


--H2_safe_q[5] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[5] at LC_X22_Y5_N6
--operation mode is arithmetic

H2_safe_q[5]_carry_eqn = (!H2L11 & H2L15) # (H2L11 & H2L16);
H2_safe_q[5]_lut_out = H2_safe_q[5] $ (E1_valid_wreq & H2_safe_q[5]_carry_eqn);
H2_safe_q[5] = DFFEAS(H2_safe_q[5]_lut_out, GLOBAL(clock), VCC, , , , , , );

--H2L18 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella5~COUT at LC_X22_Y5_N6
--operation mode is arithmetic

H2L18_cout_0 = !H2L15 # !H2_safe_q[5];
H2L18 = CARRY(H2L18_cout_0);

--H2L19 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella5~COUTCOUT1_2 at LC_X22_Y5_N6
--operation mode is arithmetic

H2L19_cout_1 = !H2L16 # !H2_safe_q[5];
H2L19 = CARRY(H2L19_cout_1);


--H2_safe_q[6] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[6] at LC_X22_Y5_N7
--operation mode is normal

H2_safe_q[6]_carry_eqn = (!H2L11 & H2L18) # (H2L11 & H2L19);
H2_safe_q[6]_lut_out = H2_safe_q[6] $ (!H2_safe_q[6]_carry_eqn & E1_valid_wreq);
H2_safe_q[6] = DFFEAS(H2_safe_q[6]_lut_out, GLOBAL(clock), VCC, , , , , , );


--H1_safe_q[0] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[0] at LC_X21_Y5_N1
--operation mode is arithmetic

H1_safe_q[0]_lut_out = E1_valid_rreq $ H1_safe_q[0];
H1_safe_q[0] = DFFEAS(H1_safe_q[0]_lut_out, GLOBAL(clock), VCC, , , , , , );

--H1L2 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella0~COUT at LC_X21_Y5_N1
--operation mode is arithmetic

H1L2_cout_0 = H1_safe_q[0];
H1L2 = CARRY(H1L2_cout_0);

--H1L3 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella0~COUTCOUT1_3 at LC_X21_Y5_N1
--operation mode is arithmetic

H1L3_cout_1 = H1_safe_q[0];
H1L3 = CARRY(H1L3_cout_1);


--H1_safe_q[1] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[1] at LC_X21_Y5_N2
--operation mode is arithmetic

H1_safe_q[1]_lut_out = H1_safe_q[1] $ (E1_valid_rreq & H1L2);
H1_safe_q[1] = DFFEAS(H1_safe_q[1]_lut_out, GLOBAL(clock), VCC, , , , , , );

--H1L5 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella1~COUT at LC_X21_Y5_N2
--operation mode is arithmetic

H1L5_cout_0 = !H1L2 # !H1_safe_q[1];
H1L5 = CARRY(H1L5_cout_0);

--H1L6 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella1~COUTCOUT1_2 at LC_X21_Y5_N2
--operation mode is arithmetic

H1L6_cout_1 = !H1L3 # !H1_safe_q[1];
H1L6 = CARRY(H1L6_cout_1);


--H1_safe_q[2] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[2] at LC_X21_Y5_N3
--operation mode is arithmetic

H1_safe_q[2]_lut_out = H1_safe_q[2] $ (E1_valid_rreq & !H1L5);
H1_safe_q[2] = DFFEAS(H1_safe_q[2]_lut_out, GLOBAL(clock), VCC, , , , , , );

--H1L8 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella2~COUT at LC_X21_Y5_N3
--operation mode is arithmetic

H1L8_cout_0 = H1_safe_q[2] & (!H1L5);
H1L8 = CARRY(H1L8_cout_0);

--H1L9 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella2~COUTCOUT1 at LC_X21_Y5_N3
--operation mode is arithmetic

H1L9_cout_1 = H1_safe_q[2] & (!H1L6);
H1L9 = CARRY(H1L9_cout_1);


--H1_safe_q[3] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[3] at LC_X21_Y5_N4
--operation mode is arithmetic

H1_safe_q[3]_lut_out = H1_safe_q[3] $ (E1_valid_rreq & H1L8);
H1_safe_q[3] = DFFEAS(H1_safe_q[3]_lut_out, GLOBAL(clock), VCC, , , , , , );

--H1L11 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella3~COUT at LC_X21_Y5_N4
--operation mode is arithmetic

H1L11 = H1L12;


--H1_safe_q[4] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[4] at LC_X21_Y5_N5
--operation mode is arithmetic

H1_safe_q[4]_carry_eqn = (!H1L11 & GND) # (H1L11 & VCC);
H1_safe_q[4]_lut_out = H1_safe_q[4] $ (E1_valid_rreq & !H1_safe_q[4]_carry_eqn);
H1_safe_q[4] = DFFEAS(H1_safe_q[4]_lut_out, GLOBAL(clock), VCC, , , , , , );

--H1L15 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella4~COUT at LC_X21_Y5_N5
--operation mode is arithmetic

H1L15_cout_0 = H1_safe_q[4] & !H1L11;
H1L15 = CARRY(H1L15_cout_0);

--H1L16 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella4~COUTCOUT1_2 at LC_X21_Y5_N5
--operation mode is arithmetic

H1L16_cout_1 = H1_safe_q[4] & !H1L11;
H1L16 = CARRY(H1L16_cout_1);


--H1_safe_q[5] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[5] at LC_X21_Y5_N6
--operation mode is arithmetic

H1_safe_q[5]_carry_eqn = (!H1L11 & H1L15) # (H1L11 & H1L16);
H1_safe_q[5]_lut_out = H1_safe_q[5] $ (E1_valid_rreq & H1_safe_q[5]_carry_eqn);
H1_safe_q[5] = DFFEAS(H1_safe_q[5]_lut_out, GLOBAL(clock), VCC, , , , , , );

--H1L18 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella5~COUT at LC_X21_Y5_N6
--operation mode is arithmetic