t2t.map.eqn

用VHDL实现的通信滑码处理

H1_safe_q[6] = DFFEAS(H1_safe_q[6]_lut_out, clock, VCC, , , , , , );


--c3flag is c3flag
--operation mode is normal

c3flag_lut_out = C3 & (c3flag & !read # !c3i) # !C3 & c3flag & !read & !c3i;
c3flag = DFFEAS(c3flag_lut_out, C8, VCC, , , , , , );


--c2flag is c2flag
--operation mode is normal

c2flag_lut_out = C2 & (c2flag & !write # !c2i) # !C2 & c2flag & !write & !c2i;
c2flag = DFFEAS(c2flag_lut_out, C8, VCC, , , , , , );


--A1L21 is datai[0]~134
--operation mode is normal

A1L21 = c3flag & (!sts[1] & !c2flag);


--startSend is startSend
--operation mode is normal

startSend_lut_out = startSend & (A1L36 # !A1L22) # !startSend & (A1L22 & !A1L32);
startSend = DFFEAS(startSend_lut_out, C8, VCC, , , , , , );


--A1L41 is sts[1]~196
--operation mode is normal

A1L41 = c3flag & !sts[1] & !c2flag & !startSend;


--J1_safe_q[6] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|cntr_cd7:count_usedw|safe_q[6]
--operation mode is normal

J1_safe_q[6]_carry_eqn = J1L12;
J1_safe_q[6]_lut_out = J1_safe_q[6] $ (!J1_safe_q[6]_carry_eqn);
J1_safe_q[6] = DFFEAS(J1_safe_q[6]_lut_out, clock, VCC, , F1L1, , , , );


--J1_safe_q[5] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|cntr_cd7:count_usedw|safe_q[5]
--operation mode is arithmetic

J1_safe_q[5]_carry_eqn = J1L10;
J1_safe_q[5]_lut_out = J1_safe_q[5] $ (J1_safe_q[5]_carry_eqn);
J1_safe_q[5] = DFFEAS(J1_safe_q[5]_lut_out, clock, VCC, , F1L1, , , , );

--J1L12 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|cntr_cd7:count_usedw|counter_cella5~COUT
--operation mode is arithmetic

J1L12 = CARRY(J1_safe_q[5] $ E1_valid_wreq # !J1L10);


--J1_safe_q[4] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|cntr_cd7:count_usedw|safe_q[4]
--operation mode is arithmetic

J1_safe_q[4]_carry_eqn = J1L8;
J1_safe_q[4]_lut_out = J1_safe_q[4] $ (!J1_safe_q[4]_carry_eqn);
J1_safe_q[4] = DFFEAS(J1_safe_q[4]_lut_out, clock, VCC, , F1L1, , , , );

--J1L10 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|cntr_cd7:count_usedw|counter_cella4~COUT
--operation mode is arithmetic

J1L10 = CARRY(!J1L8 & (J1_safe_q[4] $ !E1_valid_wreq));


--A1L32 is rtl~26
--operation mode is normal

A1L32 = !J1_safe_q[6] & !J1_safe_q[5] & !J1_safe_q[4];


--A1L22 is datai[0]~135
--operation mode is normal

A1L22 = c3flag & !sts[1] & !sts[0] & !c2flag;


--A1L39 is sts[0]~198
--operation mode is normal

A1L39 = !sts[1] & !c2flag;


--F1L3 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|b_full~85
--operation mode is normal

F1L3 = J1_safe_q[6] & write & F1_b_non_empty & !read;


--J1_safe_q[0] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|cntr_cd7:count_usedw|safe_q[0]
--operation mode is arithmetic

J1_safe_q[0]_lut_out = !J1_safe_q[0];
J1_safe_q[0] = DFFEAS(J1_safe_q[0]_lut_out, clock, VCC, , F1L1, , , , );

--J1L2 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|cntr_cd7:count_usedw|counter_cella0~COUT
--operation mode is arithmetic

J1L2 = CARRY(J1_safe_q[0] $ !E1_valid_wreq);


--J1_safe_q[1] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|cntr_cd7:count_usedw|safe_q[1]
--operation mode is arithmetic

J1_safe_q[1]_carry_eqn = J1L2;
J1_safe_q[1]_lut_out = J1_safe_q[1] $ (J1_safe_q[1]_carry_eqn);
J1_safe_q[1] = DFFEAS(J1_safe_q[1]_lut_out, clock, VCC, , F1L1, , , , );

--J1L4 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|cntr_cd7:count_usedw|counter_cella1~COUT
--operation mode is arithmetic

J1L4 = CARRY(J1_safe_q[1] $ E1_valid_wreq # !J1L2);


--J1_safe_q[3] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|cntr_cd7:count_usedw|safe_q[3]
--operation mode is arithmetic

J1_safe_q[3]_carry_eqn = J1L6;
J1_safe_q[3]_lut_out = J1_safe_q[3] $ (J1_safe_q[3]_carry_eqn);
J1_safe_q[3] = DFFEAS(J1_safe_q[3]_lut_out, clock, VCC, , F1L1, , , , );

--J1L8 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|cntr_cd7:count_usedw|counter_cella3~COUT
--operation mode is arithmetic

J1L8 = CARRY(J1_safe_q[3] $ E1_valid_wreq # !J1L6);


--J1_safe_q[2] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|cntr_cd7:count_usedw|safe_q[2]
--operation mode is arithmetic

J1_safe_q[2]_carry_eqn = J1L4;
J1_safe_q[2]_lut_out = J1_safe_q[2] $ (!J1_safe_q[2]_carry_eqn);
J1_safe_q[2] = DFFEAS(J1_safe_q[2]_lut_out, clock, VCC, , F1L1, , , , );

--J1L6 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|cntr_cd7:count_usedw|counter_cella2~COUT
--operation mode is arithmetic

J1L6 = CARRY(!J1L4 & (J1_safe_q[2] $ !E1_valid_wreq));


--F1L4 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|b_full~86
--operation mode is normal

F1L4 = J1_safe_q[5] & J1_safe_q[4] & J1_safe_q[3] & J1_safe_q[2];


--F1L5 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|b_full~87
--operation mode is normal

F1L5 = J1_safe_q[0] & J1_safe_q[1] & F1L4;


--F1L7 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|b_non_empty~77
--operation mode is normal

F1L7 = J1_safe_q[3] # J1_safe_q[2] # J1_safe_q[1] # !J1_safe_q[0];


--F1L8 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|b_non_empty~78
--operation mode is normal

F1L8 = F1L7 # !A1L32 # !read;


--c3i is c3i
--operation mode is normal

c3i_lut_out = C3;
c3i = DFFEAS(c3i_lut_out, C8, VCC, , , , , , );


--c2i is c2i
--operation mode is normal

c2i_lut_out = C2;
c2i = DFFEAS(c2i_lut_out, C8, VCC, , , , , , );


--cnt[3] is cnt[3]
--operation mode is normal

cnt[3]_lut_out = startSend & (cnt[3] $ (cnt[2] & A1L1));
cnt[3] = DFFEAS(cnt[3]_lut_out, C8, VCC, , A1L15, , , , );


--cnt[2] is cnt[2]
--operation mode is normal

cnt[2]_lut_out = startSend & (cnt[2] $ (cnt[1] & cnt[0]));
cnt[2] = DFFEAS(cnt[2]_lut_out, C8, VCC, , A1L15, , , , );


--cnt[1] is cnt[1]
--operation mode is normal

cnt[1]_lut_out = startSend & (cnt[1] $ cnt[0]);
cnt[1] = DFFEAS(cnt[1]_lut_out, C8, VCC, , A1L15, , , , );


--cnt[0] is cnt[0]
--operation mode is normal

cnt[0]_lut_out = !cnt[0] & (startSend);
cnt[0] = DFFEAS(cnt[0]_lut_out, C8, VCC, , A1L15, , , , );


--A1L36 is startSend~213
--operation mode is normal

A1L36 = !cnt[0] # !cnt[1] # !cnt[2] # !cnt[3];


--F1L1 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|_~28
--operation mode is normal

F1L1 = read & (F1_b_non_empty $ (!F1_b_full & write)) # !read & (!F1_b_full & write);


--A1L1 is add~112
--operation mode is normal

A1L1 = cnt[1] & cnt[0];


--A1L15 is cnt[3]~79
--operation mode is normal

A1L15 = A1L22 & (startSend # !A1L32);


--C8 is C8
--operation mode is input

C8 = INPUT();


--data[0] is data[0]
--operation mode is input

data[0] = INPUT();


--C3 is C3
--operation mode is input

C3 = INPUT();


--C2 is C2
--operation mode is input

C2 = INPUT();


--dataout[0] is dataout[0]
--operation mode is output

dataout[0] = OUTPUT(A1L27Q);


--q[0] is q[0]
--operation mode is output

q[0] = OUTPUT(K1_q_b[0]);


--COUT is COUT
--operation mode is output

COUT = OUTPUT(clock);


--RD is RD
--operation mode is output

RD = OUTPUT(read);


--WR is WR
--operation mode is output

WR = OUTPUT(write);


--slot is slot
--operation mode is output

slot = OUTPUT(sloti);