t2t.map.eqn

用VHDL实现的通信滑码处理

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--A1L27Q is dataout[0]~reg0
--operation mode is normal

A1L27Q_lut_out = A1L26 & (write & A1L27Q # !write & (A1L25)) # !A1L26 & A1L27Q;
A1L27Q = DFFEAS(A1L27Q_lut_out, C8, VCC, , , , , , );


--K1_q_b[0] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|dpram_17k:FIFOram|altsyncram_sga1:altsyncram1|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 1, Port B Logical Depth: 128, Port B Logical Width: 1
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
K1_q_b[0]_PORT_A_data_in = data[0];
K1_q_b[0]_PORT_A_data_in_reg = DFFE(K1_q_b[0]_PORT_A_data_in, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_A_address = BUS(H2_safe_q[0], H2_safe_q[1], H2_safe_q[2], H2_safe_q[3], H2_safe_q[4], H2_safe_q[5], H2_safe_q[6]);
K1_q_b[0]_PORT_A_address_reg = DFFE(K1_q_b[0]_PORT_A_address, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_address = BUS(H1_safe_q[0], H1_safe_q[1], H1_safe_q[2], H1_safe_q[3], H1_safe_q[4], H1_safe_q[5], H1_safe_q[6]);
K1_q_b[0]_PORT_B_address_reg = DFFE(K1_q_b[0]_PORT_B_address, K1_q_b[0]_clock_1, , , K1_q_b[0]_clock_enable_1);
K1_q_b[0]_PORT_A_write_enable = VCC;
K1_q_b[0]_PORT_A_write_enable_reg = DFFE(K1_q_b[0]_PORT_A_write_enable, K1_q_b[0]_clock_0, , , K1_q_b[0]_clock_enable_0);
K1_q_b[0]_PORT_B_read_enable = VCC;
K1_q_b[0]_PORT_B_read_enable_reg = DFFE(K1_q_b[0]_PORT_B_read_enable, K1_q_b[0]_clock_1, , , K1_q_b[0]_clock_enable_1);
K1_q_b[0]_clock_0 = clock;
K1_q_b[0]_clock_1 = clock;
K1_q_b[0]_clock_enable_0 = E1_valid_wreq;
K1_q_b[0]_clock_enable_1 = E1_valid_rreq;
K1_q_b[0]_PORT_B_data_out = MEMORY(K1_q_b[0]_PORT_A_data_in_reg, , K1_q_b[0]_PORT_A_address_reg, K1_q_b[0]_PORT_B_address_reg, K1_q_b[0]_PORT_A_write_enable_reg, K1_q_b[0]_PORT_B_read_enable_reg, , , K1_q_b[0]_clock_0, K1_q_b[0]_clock_1, K1_q_b[0]_clock_enable_0, K1_q_b[0]_clock_enable_1, , );
K1_q_b[0] = K1_q_b[0]_PORT_B_data_out[0];


--clock is clock
--operation mode is normal

clock_lut_out = clock & (sts[0] # !sts[1]) # !clock & sts[0] & (!sts[1]);
clock = DFFEAS(clock_lut_out, C8, VCC, , , , , , );


--read is read
--operation mode is normal

read_lut_out = A1L21 & (read # sts[1] $ !sts[0]) # !A1L21 & read & (!sts[0] # !sts[1]);
read = DFFEAS(read_lut_out, C8, VCC, , , , , , );


--write is write
--operation mode is normal

write_lut_out = write & (!sts[0] # !sts[1]) # !write & c2flag & !sts[1] & !sts[0];
write = DFFEAS(write_lut_out, C8, VCC, , , , , , );


--sloti is sloti
--operation mode is normal

sloti_lut_out = A1L41 & (sloti # sts[1] $ !sts[0]) # !A1L41 & sloti & (!sts[0] # !sts[1]);
sloti = DFFEAS(sloti_lut_out, C8, VCC, , , , , , );


--datai[0] is datai[0]
--operation mode is normal

datai[0]_lut_out = A1L22 & (startSend & datai[0] # !startSend & (A1L32)) # !A1L22 & datai[0];
datai[0] = DFFEAS(datai[0]_lut_out, C8, VCC, , , , , , );


--A1L25 is dataout[0]~178
--operation mode is normal

A1L25 = sloti & datai[0] # !sloti & (K1_q_b[0]);


--sts[1] is sts[1]
--operation mode is normal

sts[1]_lut_out = A1L41 # sts[1] $ sts[0];
sts[1] = DFFEAS(sts[1]_lut_out, C8, VCC, , , , , , );


--sts[0] is sts[0]
--operation mode is normal

sts[0]_lut_out = !sts[0] & (c3flag & startSend # !A1L39);
sts[0] = DFFEAS(sts[0]_lut_out, C8, VCC, , , , , , );


--A1L26 is dataout[0]~179
--operation mode is normal

A1L26 = sts[1] & sts[0];


--F1_b_full is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|b_full
--operation mode is normal

F1_b_full_lut_out = F1L3 & (F1L5 # F1_b_full & !read) # !F1L3 & (F1_b_full & !read);
F1_b_full = DFFEAS(F1_b_full_lut_out, clock, VCC, , , , , , );


--E1_valid_wreq is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|valid_wreq
--operation mode is normal

E1_valid_wreq = write & (!F1_b_full);


--F1_b_non_empty is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|a_fefifo_t7f:fifo_state|b_non_empty
--operation mode is normal

F1_b_non_empty_lut_out = write # F1_b_full # F1_b_non_empty & F1L8;
F1_b_non_empty = DFFEAS(F1_b_non_empty_lut_out, clock, VCC, , , , , , );


--E1_valid_rreq is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|valid_rreq
--operation mode is normal

E1_valid_rreq = read & F1_b_non_empty;


--H2_safe_q[0] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[0]
--operation mode is arithmetic

H2_safe_q[0]_lut_out = H2_safe_q[0] $ E1_valid_wreq;
H2_safe_q[0] = DFFEAS(H2_safe_q[0]_lut_out, clock, VCC, , , , , , );

--H2L2 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella0~COUT
--operation mode is arithmetic

H2L2 = CARRY(H2_safe_q[0]);


--H2_safe_q[1] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[1]
--operation mode is arithmetic

H2_safe_q[1]_carry_eqn = H2L2;
H2_safe_q[1]_lut_out = H2_safe_q[1] $ (E1_valid_wreq & H2_safe_q[1]_carry_eqn);
H2_safe_q[1] = DFFEAS(H2_safe_q[1]_lut_out, clock, VCC, , , , , , );

--H2L4 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella1~COUT
--operation mode is arithmetic

H2L4 = CARRY(!H2L2 # !H2_safe_q[1]);


--H2_safe_q[2] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[2]
--operation mode is arithmetic

H2_safe_q[2]_carry_eqn = H2L4;
H2_safe_q[2]_lut_out = H2_safe_q[2] $ (E1_valid_wreq & !H2_safe_q[2]_carry_eqn);
H2_safe_q[2] = DFFEAS(H2_safe_q[2]_lut_out, clock, VCC, , , , , , );

--H2L6 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella2~COUT
--operation mode is arithmetic

H2L6 = CARRY(H2_safe_q[2] & (!H2L4));


--H2_safe_q[3] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[3]
--operation mode is arithmetic

H2_safe_q[3]_carry_eqn = H2L6;
H2_safe_q[3]_lut_out = H2_safe_q[3] $ (E1_valid_wreq & H2_safe_q[3]_carry_eqn);
H2_safe_q[3] = DFFEAS(H2_safe_q[3]_lut_out, clock, VCC, , , , , , );

--H2L8 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella3~COUT
--operation mode is arithmetic

H2L8 = CARRY(!H2L6 # !H2_safe_q[3]);


--H2_safe_q[4] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[4]
--operation mode is arithmetic

H2_safe_q[4]_carry_eqn = H2L8;
H2_safe_q[4]_lut_out = H2_safe_q[4] $ (E1_valid_wreq & !H2_safe_q[4]_carry_eqn);
H2_safe_q[4] = DFFEAS(H2_safe_q[4]_lut_out, clock, VCC, , , , , , );

--H2L10 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella4~COUT
--operation mode is arithmetic

H2L10 = CARRY(H2_safe_q[4] & (!H2L8));


--H2_safe_q[5] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[5]
--operation mode is arithmetic

H2_safe_q[5]_carry_eqn = H2L10;
H2_safe_q[5]_lut_out = H2_safe_q[5] $ (E1_valid_wreq & H2_safe_q[5]_carry_eqn);
H2_safe_q[5] = DFFEAS(H2_safe_q[5]_lut_out, clock, VCC, , , , , , );

--H2L12 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|counter_cella5~COUT
--operation mode is arithmetic

H2L12 = CARRY(!H2L10 # !H2_safe_q[5]);


--H2_safe_q[6] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:wr_ptr|safe_q[6]
--operation mode is normal

H2_safe_q[6]_carry_eqn = H2L12;
H2_safe_q[6]_lut_out = H2_safe_q[6] $ (E1_valid_wreq & !H2_safe_q[6]_carry_eqn);
H2_safe_q[6] = DFFEAS(H2_safe_q[6]_lut_out, clock, VCC, , , , , , );


--H1_safe_q[0] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[0]
--operation mode is arithmetic

H1_safe_q[0]_lut_out = H1_safe_q[0] $ E1_valid_rreq;
H1_safe_q[0] = DFFEAS(H1_safe_q[0]_lut_out, clock, VCC, , , , , , );

--H1L2 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella0~COUT
--operation mode is arithmetic

H1L2 = CARRY(H1_safe_q[0]);


--H1_safe_q[1] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[1]
--operation mode is arithmetic

H1_safe_q[1]_carry_eqn = H1L2;
H1_safe_q[1]_lut_out = H1_safe_q[1] $ (E1_valid_rreq & H1_safe_q[1]_carry_eqn);
H1_safe_q[1] = DFFEAS(H1_safe_q[1]_lut_out, clock, VCC, , , , , , );

--H1L4 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella1~COUT
--operation mode is arithmetic

H1L4 = CARRY(!H1L2 # !H1_safe_q[1]);


--H1_safe_q[2] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[2]
--operation mode is arithmetic

H1_safe_q[2]_carry_eqn = H1L4;
H1_safe_q[2]_lut_out = H1_safe_q[2] $ (E1_valid_rreq & !H1_safe_q[2]_carry_eqn);
H1_safe_q[2] = DFFEAS(H1_safe_q[2]_lut_out, clock, VCC, , , , , , );

--H1L6 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella2~COUT
--operation mode is arithmetic

H1L6 = CARRY(H1_safe_q[2] & (!H1L4));


--H1_safe_q[3] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[3]
--operation mode is arithmetic

H1_safe_q[3]_carry_eqn = H1L6;
H1_safe_q[3]_lut_out = H1_safe_q[3] $ (E1_valid_rreq & H1_safe_q[3]_carry_eqn);
H1_safe_q[3] = DFFEAS(H1_safe_q[3]_lut_out, clock, VCC, , , , , , );

--H1L8 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella3~COUT
--operation mode is arithmetic

H1L8 = CARRY(!H1L6 # !H1_safe_q[3]);


--H1_safe_q[4] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[4]
--operation mode is arithmetic

H1_safe_q[4]_carry_eqn = H1L8;
H1_safe_q[4]_lut_out = H1_safe_q[4] $ (E1_valid_rreq & !H1_safe_q[4]_carry_eqn);
H1_safe_q[4] = DFFEAS(H1_safe_q[4]_lut_out, clock, VCC, , , , , , );

--H1L10 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella4~COUT
--operation mode is arithmetic

H1L10 = CARRY(H1_safe_q[4] & (!H1L8));


--H1_safe_q[5] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[5]
--operation mode is arithmetic

H1_safe_q[5]_carry_eqn = H1L10;
H1_safe_q[5]_lut_out = H1_safe_q[5] $ (E1_valid_rreq & H1_safe_q[5]_carry_eqn);
H1_safe_q[5] = DFFEAS(H1_safe_q[5]_lut_out, clock, VCC, , , , , , );

--H1L12 is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|counter_cella5~COUT
--operation mode is arithmetic

H1L12 = CARRY(!H1L10 # !H1_safe_q[5]);


--H1_safe_q[6] is lpm_fifo:U1|scfifo:myFIFO|scfifo_sin:auto_generated|a_dpfifo_pek:dpfifo|cntr_ue8:rd_ptr_count|safe_q[6]
--operation mode is normal

H1_safe_q[6]_carry_eqn = H1L12;
H1_safe_q[6]_lut_out = H1_safe_q[6] $ (E1_valid_rreq & !H1_safe_q[6]_carry_eqn);