📄 r2r.rpt
字号:
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 0 3 7 8 0 8 8 8 8 0 8 8 8 8 7 0 2 8 8 8 8 8 8 2 141/8
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 8 3 6 8 8 3 8 6 6 8 7 8 8 8 8 8 8 8 3 8 2 8 8 7 8 163/8
Total: 16 3 9 15 16 3 16 14 14 16 7 16 16 16 16 15 8 10 11 16 10 16 16 15 10 304/16
Device-Specific Information: k:\vhdl\n\n\t2t\r2r.rpt
r2r
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
43 - - - -- INPUT G 0 0 0 2 C2
17 - - A -- INPUT 0 0 0 2 C3
1 - - - -- INPUT G 0 0 0 0 C8
84 - - - -- INPUT 0 0 0 4 data0
58 - - C -- INPUT 0 0 0 4 data1
61 - - C -- INPUT 0 0 0 4 data2
44 - - - -- INPUT 0 0 0 4 data3
2 - - - -- INPUT 0 0 0 4 data4
42 - - - -- INPUT 0 0 0 4 data5
35 - - - 06 INPUT 0 0 0 4 data6
37 - - - 09 INPUT 0 0 0 4 data7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: k:\vhdl\n\n\t2t\r2r.rpt
r2r
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
50 - - - 17 OUTPUT 0 1 0 0 COUT
28 - - C -- OUTPUT 0 1 0 0 dataout0
27 - - C -- OUTPUT 0 1 0 0 dataout1
30 - - C -- OUTPUT 0 1 0 0 dataout2
60 - - C -- OUTPUT 0 1 0 0 dataout3
29 - - C -- OUTPUT 0 1 0 0 dataout4
62 - - C -- OUTPUT 0 1 0 0 dataout5
54 - - - 21 OUTPUT 0 1 0 0 dataout6
59 - - C -- OUTPUT 0 1 0 0 dataout7
18 - - A -- OUTPUT 0 1 0 0 q0
69 - - A -- OUTPUT 0 1 0 0 q1
73 - - A -- OUTPUT 0 1 0 0 q2
81 - - - 22 OUTPUT 0 1 0 0 q3
70 - - A -- OUTPUT 0 1 0 0 q4
71 - - A -- OUTPUT 0 1 0 0 q5
72 - - A -- OUTPUT 0 1 0 0 q6
25 - - B -- OUTPUT 0 0 0 0 q7
52 - - - 19 OUTPUT 0 1 0 0 RD
19 - - A -- OUTPUT 0 1 0 0 slot
48 - - - 15 OUTPUT 0 1 0 0 WR
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: k:\vhdl\n\n\t2t\r2r.rpt
r2r
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - A 13 OR2 ! 0 2 0 2 |LPM_ADD_SUB:378|addcore:adder|:59
- 5 - A 13 OR2 ! 0 3 0 2 |LPM_ADD_SUB:378|addcore:adder|:63
- 5 - A 15 DFFE 0 3 0 3 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|b_full
- 7 - A 15 DFFE 0 3 0 3 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|b_non_empty
- 5 - A 21 DFFE 0 3 1 4 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|dffs0
- 8 - A 21 DFFE 0 4 1 3 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|dffs1
- 1 - A 21 DFFE 0 4 1 4 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|dffs2
- 6 - A 21 DFFE 0 4 1 3 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|dffs3
- 5 - A 23 DFFE 0 4 1 4 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|dffs4
- 4 - A 23 DFFE 0 4 1 3 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|dffs5
- 3 - A 23 DFFE 0 4 1 2 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|dffs6
- 4 - A 21 OR2 0 3 0 3 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|lpm_add_sub:add_sub|addcore:adder|pcarry1
- 7 - A 21 OR2 0 3 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|lpm_add_sub:add_sub|addcore:adder|pcarry2
- 2 - A 21 OR2 0 4 0 3 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|lpm_add_sub:add_sub|addcore:adder|pcarry3
- 2 - A 23 OR2 0 3 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|lpm_add_sub:add_sub|addcore:adder|pcarry4
- 7 - A 23 OR2 0 4 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:56|lpm_add_sub:add_sub|addcore:adder|pcarry5
- 3 - A 21 OR2 s 0 4 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|~158~1
- 8 - A 23 OR2 s 0 4 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|~158~2
- 1 - A 23 AND2 s 0 4 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|~169~1
- 6 - A 23 AND2 s 0 4 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|~169~2
- 6 - A 15 OR2 s 0 4 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|~190~1
- 3 - A 15 OR2 s 0 4 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|~192~1
- 8 - C 13 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs0
- 8 - C 07 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs1
- 7 - C 12 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs2
- 2 - C 01 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs3
- 1 - C 04 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs4
- 7 - C 16 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs5
- 5 - C 23 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs6
- 7 - C 21 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|dffs7
- 7 - C 13 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs0
- 7 - C 07 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs1
- 6 - C 12 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs2
- 8 - C 01 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs3
- 8 - C 04 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs4
- 6 - C 16 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs5
- 4 - C 19 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs6
- 6 - C 21 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|dffs7
- 6 - C 13 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs0
- 5 - C 07 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs1
- 5 - C 12 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs2
- 7 - C 01 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs3
- 7 - C 04 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs4
- 5 - C 16 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs5
- 8 - C 19 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs6
- 5 - C 21 DFFE 0 5 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|dffs7
- 5 - C 13 DFFE 0 3 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:137|dffs0
- 4 - C 07 DFFE 0 3 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:137|dffs1
- 8 - C 18 DFFE 0 3 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:137|dffs2
- 6 - C 01 DFFE 0 3 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:137|dffs3
- 6 - C 04 DFFE 0 3 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:137|dffs4
- 2 - C 18 DFFE 0 3 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:137|dffs5
- 7 - C 19 DFFE 0 3 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:137|dffs6
- 4 - C 18 DFFE 0 3 0 1 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:137|dffs7
- 8 - C 14 DFFE 0 5 0 12 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:163|dffs0
- 7 - C 14 DFFE 0 5 0 11 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:163|dffs1
- 3 - C 14 DFFE 0 4 0 4 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|pipefull0
- 2 - C 19 DFFE 0 5 0 11 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|pipefull3
- 3 - C 19 OR2 0 2 0 10 |LPM_FIFO:U1|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|:220
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