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📄 r2r.rpt

📁 用VHDL实现的通信滑码处理
💻 RPT
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                R  R  R  R  R  R  R     R           R        R  R  R     O     
                E  E  E  E  E  E  E     E           E        E  E  E     N     
                S  S  S  S  S  S  S  V  S           S  G     S  S  S     F     
                E  E  E  E  E  E  E  C  E  d     d  E  N     E  E  E     _  ^  
                R  R  R  R  R  R  R  C  R  a     a  R  D     R  R  R  #  D  n  
                V  V  V  V  V  V  V  I  V  t     t  V  I     V  V  V  T  O  C  
                E  E  E  E  E  E  E  N  E  a  C  a  E  N  q  E  E  E  C  N  E  
                D  D  D  D  D  D  D  T  D  4  8  0  D  T  3  D  D  D  K  E  O  
              -----------------------------------------------------------------_ 
            /  11 10  9  8  7  6  5  4  3  2  1 84 83 82 81 80 79 78 77 76 75   | 
    ^DATA0 | 12                                                              74 | #TDO 
     ^DCLK | 13                                                              73 | q2 
      ^nCE | 14                                                              72 | q6 
      #TDI | 15                                                              71 | q5 
  RESERVED | 16                                                              70 | q4 
        C3 | 17                                                              69 | q1 
        q0 | 18                                                              68 | GNDINT 
      slot | 19                                                              67 | RESERVED 
    VCCINT | 20                                                              66 | RESERVED 
  RESERVED | 21                                                              65 | RESERVED 
  RESERVED | 22                        EPF10K10LC84-3                        64 | RESERVED 
  RESERVED | 23                                                              63 | VCCINT 
  RESERVED | 24                                                              62 | dataout5 
        q7 | 25                                                              61 | data2 
    GNDINT | 26                                                              60 | dataout3 
  dataout1 | 27                                                              59 | dataout7 
  dataout0 | 28                                                              58 | data1 
  dataout4 | 29                                                              57 | #TMS 
  dataout2 | 30                                                              56 | #TRST 
    ^MSEL0 | 31                                                              55 | ^nSTATUS 
    ^MSEL1 | 32                                                              54 | dataout6 
           |_  33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53  _| 
             ------------------------------------------------------------------ 
                V  ^  d  R  d  R  R  V  G  d  C  d  V  G  R  W  R  C  R  R  R  
                C  n  a  E  a  E  E  C  N  a  2  a  C  N  E  R  E  O  E  D  E  
                C  C  t  S  t  S  S  C  D  t     t  C  D  S     S  U  S     S  
                I  O  a  E  a  E  E  I  I  a     a  I  I  E     E  T  E     E  
                N  N  6  R  7  R  R  N  N  5     3  N  N  R     R     R     R  
                T  F     V     V  V  T  T           T  T  V     V     V     V  
                   I     E     E  E                       E     E     E     E  
                   G     D     D  D                       D     D     D     D  
                                                                               
                                                                               


N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:                           k:\vhdl\n\n\t2t\r2r.rpt
r2r

** RESOURCE USAGE **

Logic                Column       Row                                   
Array                Interconnect Interconnect         Clears/     External  
Block   Logic Cells  Driven       Driven       Clocks  Presets   Interconnect
A1       8/ 8(100%)   5/ 8( 62%)   4/ 8( 50%)    1/2    0/2       8/22( 36%)   
A3       3/ 8( 37%)   2/ 8( 25%)   2/ 8( 25%)    1/2    0/2       3/22( 13%)   
A4       7/ 8( 87%)   2/ 8( 25%)   3/ 8( 37%)    1/2    0/2       3/22( 13%)   
A5       8/ 8(100%)   3/ 8( 37%)   4/ 8( 50%)    1/2    0/2       8/22( 36%)   
A7       8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    1/2    0/2      12/22( 54%)   
A8       8/ 8(100%)   1/ 8( 12%)   4/ 8( 50%)    1/2    0/2       6/22( 27%)   
A9       8/ 8(100%)   1/ 8( 12%)   6/ 8( 75%)    1/2    0/2       7/22( 31%)   
A10      8/ 8(100%)   3/ 8( 37%)   2/ 8( 25%)    1/2    0/2      14/22( 63%)   
A12      8/ 8(100%)   1/ 8( 12%)   6/ 8( 75%)    1/2    0/2       7/22( 31%)   
A13      8/ 8(100%)   0/ 8(  0%)   1/ 8( 12%)    1/2    0/2       6/22( 27%)   
A14      8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    1/2    0/2       8/22( 36%)   
A15      7/ 8( 87%)   4/ 8( 50%)   3/ 8( 37%)    2/2    0/2       7/22( 31%)   
A17      2/ 8( 25%)   3/ 8( 37%)   1/ 8( 12%)    1/2    0/2       3/22( 13%)   
A18      8/ 8(100%)   0/ 8(  0%)   6/ 8( 75%)    1/2    0/2       6/22( 27%)   
A19      8/ 8(100%)   0/ 8(  0%)   3/ 8( 37%)    1/2    0/2       6/22( 27%)   
A20      8/ 8(100%)   1/ 8( 12%)   5/ 8( 62%)    1/2    0/2       5/22( 22%)   
A21      8/ 8(100%)   1/ 8( 12%)   6/ 8( 75%)    1/2    0/2       5/22( 22%)   
A22      8/ 8(100%)   2/ 8( 25%)   5/ 8( 62%)    1/2    0/2       9/22( 40%)   
A23      8/ 8(100%)   0/ 8(  0%)   5/ 8( 62%)    1/2    0/2       9/22( 40%)   
A24      2/ 8( 25%)   1/ 8( 12%)   1/ 8( 12%)    1/2    0/2       5/22( 22%)   
C1       8/ 8(100%)   0/ 8(  0%)   2/ 8( 25%)    1/2    0/2      17/22( 77%)   
C2       3/ 8( 37%)   1/ 8( 12%)   3/ 8( 37%)    1/2    0/2       5/22( 22%)   
C3       6/ 8( 75%)   1/ 8( 12%)   3/ 8( 37%)    1/2    0/2       9/22( 40%)   
C4       8/ 8(100%)   0/ 8(  0%)   2/ 8( 25%)    1/2    0/2      17/22( 77%)   
C5       8/ 8(100%)   0/ 8(  0%)   3/ 8( 37%)    1/2    0/2      11/22( 50%)   
C6       3/ 8( 37%)   0/ 8(  0%)   3/ 8( 37%)    1/2    0/2       9/22( 40%)   
C7       8/ 8(100%)   0/ 8(  0%)   2/ 8( 25%)    1/2    0/2      17/22( 77%)   
C8       6/ 8( 75%)   2/ 8( 25%)   3/ 8( 37%)    1/2    0/2       9/22( 40%)   
C9       6/ 8( 75%)   1/ 8( 12%)   3/ 8( 37%)    1/2    0/2       9/22( 40%)   
C10      8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    2/2    0/2       5/22( 22%)   
C11      7/ 8( 87%)   2/ 8( 25%)   3/ 8( 37%)    1/2    0/2      11/22( 50%)   
C12      8/ 8(100%)   0/ 8(  0%)   1/ 8( 12%)    1/2    0/2      19/22( 86%)   
C13      8/ 8(100%)   0/ 8(  0%)   1/ 8( 12%)    1/2    0/2      19/22( 86%)   
C14      8/ 8(100%)   0/ 8(  0%)   6/ 8( 75%)    1/2    0/2       4/22( 18%)   
C15      8/ 8(100%)   1/ 8( 12%)   3/ 8( 37%)    1/2    0/2      12/22( 54%)   
C16      8/ 8(100%)   0/ 8(  0%)   1/ 8( 12%)    1/2    0/2      19/22( 86%)   
C17      8/ 8(100%)   2/ 8( 25%)   4/ 8( 50%)    2/2    0/2      10/22( 45%)   
C18      3/ 8( 37%)   0/ 8(  0%)   3/ 8( 37%)    1/2    0/2       5/22( 22%)   
C19      8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    1/2    0/2      12/22( 54%)   
C20      2/ 8( 25%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2       5/22( 22%)   
C21      8/ 8(100%)   0/ 8(  0%)   1/ 8( 12%)    1/2    0/2      19/22( 86%)   
C22      8/ 8(100%)   1/ 8( 12%)   3/ 8( 37%)    2/2    0/2       5/22( 22%)   
C23      7/ 8( 87%)   0/ 8(  0%)   2/ 8( 25%)    1/2    0/2      16/22( 72%)   
C24      8/ 8(100%)   0/ 8(  0%)   6/ 8( 75%)    1/2    0/2       4/22( 18%)   


Embedded             Column       Row                                   
Array     Embedded   Interconnect Interconnect         Read/      External  
Block     Cells      Driven       Driven       Clocks  Write    Interconnect
A25      8/8 (100%)   6/8 ( 75%)   2/8 ( 25%)    1/2    2/2      16/22( 72%)   
C25      8/8 (100%)   2/8 ( 25%)   6/8 ( 75%)    1/2    2/2      16/22( 72%)   


Total dedicated input pins used:                 6/6      (100%)
Total I/O pins used:                            25/53     ( 47%)
Total logic cells used:                        304/576    ( 52%)
Total embedded cells used:                      16/24     ( 66%)
Total EABs used:                                 2/3      ( 66%)
Average fan-in:                                 3.18/4    ( 79%)
Total fan-in:                                 967/2304    ( 41%)

Total input pins required:                      11
Total input I/O cell registers required:         0
Total output pins required:                     20
Total output I/O cell registers required:        0
Total buried I/O cell registers required:        0
Total bidirectional pins required:               0
Total reserved pins required                     0
Total logic cells required:                    304
Total flipflops required:                      192
Total packed registers required:                 0
Total logic cells in carry chains:               0
Total number of carry chains:                    0
Total logic cells in cascade chains:             0
Total number of cascade chains:                  0
Total single-pin Clock Enables required:         0
Total single-pin Output Enables required:        0

Synthesized logic cells:                        28/ 576   (  4%)

Logic Cell and Embedded Cell Counts

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