div.txt

这是一个用verilog实现的除法器代码。

除法器的电路设计,基本的思想是减法:从最高位(除符号位)开始,减去除数,得到商.

       下面这个电路是一个简单的除法器,速度不快,但是可以加入pipeline来提高频率.


module  DIV (

              Clk,

              Dividend,

              Divisior,

              Quotient

            );

    input Clk;

    input [5:0] Dividend;

    input [2:0] Divisior;

    output[7:0] Quotient;

    wire  [5:0] Abs_D;

    wire  [3:0] D_P,D_M

    wire  [3:0] P4,P3,P2,P1,P0,PR,PR1,PR2;

    wire  [3:0] R4,R3,R2,R1,R0,RR,RR1,RR2;

    wire  [7:0] C;

    reg   [7:0] Quotient; 

//====================================

    assign  Abs_D = Dividend[5] ? (~Dividend +1) : Dividend;

    assign  D_P = {1'b0,Divisior};

    assign  D_M = ~{1'b0,Divisior} + 1;

//======================================

   assign P4 = { 3'b0, Abs_D[4] };

   assign R4 = P4 - D_P;

 

   assign P3 = { R4[2:0],Abs_D[3]};

   assign R3 = P3 + (~R4[3] ? D_M : D_P);

 

   assign P2 = { R3[2:0],Abs_D[2]};

   assign R2 = P2 + (~R3[3] ? D_M : D_P);

 

   assign P1 = { R2[2:0],Abs_D[1]};

   assign R1 = P1 + (~R2[3] ? D_M : D_P);


   assign P0 = { R1[2:0],Abs_D[0]};

   assign R0 = P0 + (~R1[3] ? D_M : D_P);

 

   assign PR = { R0[2:0],1'b0};

   assign RR = PR + (~R0[3] ? D_M : D_P);

 

   assign PR1 = { RR[2:0],1'b0};

   assign RR1 = PR1 + (~RR[3] ? D_M : D_P);

 

   assign PR2 = { RR1[2:0],1'b0};

   assign RR2 = PR2 + (~RR1[3] ? D_M : D_P);

 

   assign C = { ~R4[3],~R3[3],~R2[3],~R1[3],~R0[3],~RR[3],~RR1[3],~RR2[3] };

   always @(posedge Clk)

         Quotient <= Dividend[5] ? ~C + 1 : C;

endmodule