clkgen.npl

verilog 编写的pic16c5x时钟模块

JDF G
// Created by Project Navigator ver 1.0
PROJECT clkgen
DESIGN clkgen
DEVFAM spartan2e
DEVFAMTIME 0
DEVICE xc2s200e
DEVICETIME 0
DEVPKG ft256
DEVPKGTIME 0
DEVSPEED -7
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL Verilog
GENERATEDSIMULATIONMODELTIME 0
SOURCE clkgen.v
STIMULUS wave.tbw
[STRATEGY-LIST]
Normal=True