transcript

verilog 编写的pic16c5x时钟模块

# Reading C:/Modeltech_5.7c/tcl/vsim/pref.tcl 
# do wave.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vlog 5.7c Compiler 2003.03 Mar 13 2003
# -- Compiling module clkgen
# 
# Top level modules:
# 	clkgen
# Model Technology ModelSim SE vlog 5.7c Compiler 2003.03 Mar 13 2003
# -- Compiling module wave
# 
# Top level modules:
# 	wave
# Model Technology ModelSim SE vlog 5.7c Compiler 2003.03 Mar 13 2003
# -- Compiling module glbl
# 
# Top level modules:
# 	glbl
# vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps wave glbl 
# Loading work.wave
# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "E:\fpga\XilinxCoreLib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unisims_ver' at "E:\fpga\unisims_ver".
# No such file or directory. (errno = ENOENT)
# Loading work.clkgen
# ** Warning: (vsim-3009) [TSCALE] - Module 'clkgen' does not have a `timescale directive in effect, but previous modules do.
#         Region: /wave/UUT
# Loading work.glbl
# .wave
# .structure
# .signals
# No errors or warnings
# Break at wave.tfw line 92
# Simulation Breakpoint: Break at wave.tfw line 92
# MACRO ./wave.fdo PAUSED at line 14
destroy .wave
destroy .signals