clkgen.syr

verilog 编写的pic16c5x时钟模块

Release 6.2i - xst G.31a
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: clkgen.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : clkgen.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : clkgen
Output Format                      : NGC
Target Device                      : xc2s200e-7-ft256

---- Source Options
Top Module Name                    : clkgen
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : clkgen.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clkgen.v"
Module <clkgen> compiled
No errors in compilation
Analysis of file <clkgen.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clkgen>.
Module <clkgen> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clkgen>.
    Related source file is clkgen.v.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 5                                              |
    | Inputs             | 0                                              |
    | Outputs            | 5                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (negative)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 00001                                          |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <clk1>.
    Found 1-bit register for signal <clk2>.
    Found 1-bit register for signal <clk3>.
    Found 1-bit register for signal <clk4>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   4 D-type flip-flop(s).
Unit <clkgen> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <state> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Registers                        : 9
 1-bit register                    : 9

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clkgen> ...
Loading device for application Xst from file '2s200e.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clkgen, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : clkgen.ngr
Top Level Output File Name         : clkgen
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 6

Macro Statistics :
# Registers                        : 4
#      1-bit register              : 4

Cell Usage :
# BELS                             : 4
#      GND                         : 1
#      LUT1                        : 1
#      LUT2_L                      : 1
#      LUT4                        : 1
# FlipFlops/Latches                : 9
#      FDR                         : 3
#      FDRS                        : 1
#      FDRSE                       : 4
#      FDS                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 5
#      IBUF                        : 1
#      OBUF                        : 4
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200eft256-7 

 Number of Slices:                       8  out of   2352     0%  
 Number of Slice Flip Flops:             9  out of   4704     0%  
 Number of 4 input LUTs:                 3  out of   4704     0%  
 Number of bonded IOBs:                  5  out of    182     2%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 9     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -7

   Minimum period: 4.992ns (Maximum Frequency: 200.321MHz)
   Minimum input arrival time before clock: 4.466ns
   Maximum output required time after clock: 6.140ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               4.992ns (Levels of Logic = 2)
  Source:            state_FFd4 (FF)
  Destination:       clk4 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: state_FFd4 to clk4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRS:C->Q             3   0.886   1.188  state_FFd4 (state_FFd4)
     LUT2_L:I1->LO         1   0.418   0.100  _n0009_SW0 (N302)
     LUT4:I3->O            4   0.418   1.368  _n0009 (_n0009)
     FDRSE:CE                  0.614          clk4
    ----------------------------------------
    Total                      4.992ns (2.336ns logic, 2.656ns route)
                                       (46.8% logic, 53.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset:              4.466ns (Levels of Logic = 2)
  Source:            reset (PAD)
  Destination:       clk4 (FF)
  Destination Clock: clk rising

  Data Path: reset to clk4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.769   0.828  reset_IBUF (reset_IBUF)
     LUT1:I0->O            9   0.418   1.935  state_FFd4_N381 (state_FFd4_N38)
     FDRS:R                    0.516          state_FFd4
    ----------------------------------------
    Total                      4.466ns (1.703ns logic, 2.763ns route)
                                       (38.1% logic, 61.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              6.140ns (Levels of Logic = 1)
  Source:            clk1 (FF)
  Destination:       clk1 (PAD)
  Source Clock:      clk rising

  Data Path: clk1 to clk1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRSE:C->Q            1   0.886   0.828  clk1 (clk1_OBUF)
     OBUF:I->O                 4.426          clk1_OBUF (clk1)
    ----------------------------------------
    Total                      6.140ns (5.312ns logic, 0.828ns route)
                                       (86.5% logic, 13.5% route)

=========================================================================
CPU : 2.23 / 3.30 s | Elapsed : 2.00 / 3.00 s
 
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Total memory usage is 61200 kilobytes