dff.syr

verilog 编写的pic16c5x时钟模块

Release 6.2i - xst G.31a
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: dff.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : dff.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : dff
Output Format                      : NGC
Target Device                      : xc2s200e-7-ft256

---- Source Options
Top Module Name                    : dff
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : dff.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "clkgen.v"
Module <clkgen> compiled
ERROR:HDLCompilers:26 - clkgen.v line 8 expecting 'endmodule', found 'module'
ERROR:HDLCompilers:26 - clkgen.v line 46 expecting ';', found 'input'
ERROR:HDLCompilers:208 - clkgen.v line 45 Port reference 'clk' was not declared as input, inout or output
ERROR:HDLCompilers:208 - clkgen.v line 45 Port reference 'din' was not declared as input, inout or output
ERROR:HDLCompilers:208 - clkgen.v line 45 Port reference 'q' was not declared as input, inout or output
Module <dff> compiled
ERROR:HDLCompilers:26 - clkgen.v line 54 expecting ';', found 'input'
ERROR:HDLCompilers:208 - clkgen.v line 53 Port reference 'clk1' was not declared as input, inout or output
ERROR:HDLCompilers:208 - clkgen.v line 53 Port reference 'clk' was not declared as input, inout or output
ERROR:HDLCompilers:208 - clkgen.v line 53 Port reference 'din' was not declared as input, inout or output
Module <dff1> compiled
ERROR:HDLCompilers:26 - clkgen.v line 77 expecting ';', found 'input'
ERROR:HDLCompilers:208 - clkgen.v line 76 Port reference 'clk4' was not declared as input, inout or output
ERROR:HDLCompilers:208 - clkgen.v line 76 Port reference 'clk' was not declared as input, inout or output
ERROR:HDLCompilers:208 - clkgen.v line 76 Port reference 'din' was not declared as input, inout or output
Module <dff4> compiled
ERROR:HDLCompilers:26 - clkgen.v line 84 expecting 'EOF', found 'and'
Analysis of file <dff.prj> failed.
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Total memory usage is 48276 kilobytes