and2.vhd

来自「自己设计的一个简单的与门设计。新手初学」· VHDL 代码 · 共 9 行

entity and_2 is
port(x,y:in bit;
	z:out bit);
end entity and_2;

architecture exe of and_2 is
begin
	z<=x and y;
end architecture exe;