h_adder.vhd

来自「8位的加法器设计」· VHDL 代码 · 共 11 行

entity h_adder is
	port(a,b:in bit;
		r,c:out bit);
end entity h_adder;

ARCHITECTURE ex1 OF h_adder IS
BEGIN
	r<=a xor b;
	c<=a and b;
END ex1;