f_adder.vhd

来自「8位的加法器设计」· VHDL 代码 · 共 20 行

entity f_adder is
	port(ain,bin,cin:in bit;
		rout,cout:out bit);
end f_adder;

architecture ex3 of f_adder is
	component h_adder
		port(a,b:in bit;
			r,c:out bit);
	end component;
	component ior2
		port(x,y:in bit;
			z:out bit);
	end component;
	signal w,v,q:bit;
	begin
	    m0:h_adder port map(a=>ain,b=>bin,r=>w,c=>v);
		m1:h_adder port map(a=>w,b=>cin,c=>q,r=>rout);
		m2:ior2 port map(x=>v,y=>q,z=>cout);
end ex3;