pipeline_adder.syr

Self timed pipelined adder

#      OBUF                        : 5
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s100evq100-5 

 Number of Slices:                       9  out of    960     0%  
 Number of Slice Flip Flops:             8  out of   1920     0%  
 Number of 4 input LUTs:                13  out of   1920     0%  
 Number of bonded IOBs:                 11  out of     66    16%  
    IOB Flip Flops: 6


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
---------------------------------------------------------+------------------------------------+-------+
Clock Signal                                             | Clock buffer(FF name)              | Load  |
---------------------------------------------------------+------------------------------------+-------+
Structure3/HS_1/C_1/_n0009(Structure3/HS_1/C_1/_n00091:O)| NONE(*)(Structure3/HS_1/C_1/Output)| 1     |
Structure2/HS_1/C_1/Output                               | NONE                               | 2     |
Structure2/HS_1/C_2/Output                               | NONE                               | 2     |
Structure2/HS_1/C_2/_n0009(Structure2/HS_1/C_2/_n00091:O)| NONE(*)(Structure2/HS_1/C_2/Output)| 1     |
Structure2/HS_1/C_1/_n0009(Structure2/HS_1/C_1/_n00091:O)| NONE(*)(Structure2/HS_1/C_1/Output)| 1     |
Structure1/HS_1/C_1/Output                               | NONE                               | 2     |
Structure1/HS_1/C_2/Output                               | NONE                               | 3     |
Structure1/HS_1/C_2/_n0009(Structure1/HS_1/C_2/_n00091:O)| NONE(*)(Structure1/HS_1/C_2/Output)| 1     |
Structure1/HS_1/C_1/_n0009(Structure1/HS_1/C_1/_n00091:O)| NONE(*)(Structure1/HS_1/C_1/Output)| 1     |
---------------------------------------------------------+------------------------------------+-------+
(*) These 5 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 2.390ns (Maximum Frequency: 418.489MHz)
   Minimum input arrival time before clock: 3.371ns
   Maximum output required time after clock: 4.105ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'Structure1/HS_1/C_1/_n0009'
  Clock period: 2.390ns (frequency: 418.489MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               2.390ns (Levels of Logic = 1)
  Source:            Structure1/HS_1/C_1/Output (LATCH)
  Destination:       Structure1/HS_1/C_1/Output (LATCH)
  Source Clock:      Structure1/HS_1/C_1/_n0009 falling
  Destination Clock: Structure1/HS_1/C_1/_n0009 falling

  Data Path: Structure1/HS_1/C_1/Output to Structure1/HS_1/C_1/Output
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               6   0.588   0.922  Structure1/HS_1/C_1/Output (Structure1/HS_1/C_1/Output)
     LUT3_L:I1->LO         1   0.612   0.000  Structure1/HS_1/C_1/_n00011 (Structure1/HS_1/C_1/_n0001)
     LD:D                      0.268          Structure1/HS_1/C_1/Output
    ----------------------------------------
    Total                      2.390ns (1.468ns logic, 0.922ns route)
                                       (61.4% logic, 38.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Structure3/HS_1/C_1/_n0009'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              3.287ns (Levels of Logic = 2)
  Source:            Reset (PAD)
  Destination:       Structure3/HS_1/C_1/Output (LATCH)
  Destination Clock: Structure3/HS_1/C_1/_n0009 falling

  Data Path: Reset to Structure3/HS_1/C_1/Output
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            19   1.106   1.301  Reset_IBUF (Reset_IBUF)
     LUT2:I1->O            1   0.612   0.000  Structure3/HS_1/C_1/_n00011 (Structure3/HS_1/C_1/_n0001)
     LD:D                      0.268          Structure3/HS_1/C_1/Output
    ----------------------------------------
    Total                      3.287ns (1.986ns logic, 1.301ns route)
                                       (60.4% logic, 39.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Structure2/HS_1/C_1/Output'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              2.055ns (Levels of Logic = 1)
  Source:            InputA<1> (PAD)
  Destination:       Structure2/R_1/Output_0 (FF)
  Destination Clock: Structure2/HS_1/C_1/Output rising

  Data Path: InputA<1> to Structure2/R_1/Output_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.106   0.681  InputA_1_IBUF (InputA_1_IBUF)
     FDC:D                     0.268          Structure2/R_1/Output_0
    ----------------------------------------
    Total                      2.055ns (1.374ns logic, 0.681ns route)
                                       (66.9% logic, 33.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Structure2/HS_1/C_2/_n0009'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              3.371ns (Levels of Logic = 2)
  Source:            Reset (PAD)
  Destination:       Structure2/HS_1/C_2/Output (LATCH)
  Destination Clock: Structure2/HS_1/C_2/_n0009 falling

  Data Path: Reset to Structure2/HS_1/C_2/Output
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            19   1.106   1.385  Reset_IBUF (Reset_IBUF)
     LUT3:I0->O            1   0.612   0.000  Structure2/HS_1/C_2/_n00011 (Structure2/HS_1/C_2/_n0001)
     LD:D                      0.268          Structure2/HS_1/C_2/Output
    ----------------------------------------
    Total                      3.371ns (1.986ns logic, 1.385ns route)
                                       (58.9% logic, 41.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Structure2/HS_1/C_1/_n0009'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              3.371ns (Levels of Logic = 2)
  Source:            Reset (PAD)
  Destination:       Structure2/HS_1/C_1/Output (LATCH)
  Destination Clock: Structure2/HS_1/C_1/_n0009 falling

  Data Path: Reset to Structure2/HS_1/C_1/Output
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            19   1.106   1.385  Reset_IBUF (Reset_IBUF)
     LUT3:I0->O            1   0.612   0.000  Structure2/HS_1/C_1/_n00011 (Structure2/HS_1/C_1/_n0001)
     LD:D                      0.268          Structure2/HS_1/C_1/Output
    ----------------------------------------
    Total                      3.371ns (1.986ns logic, 1.385ns route)
                                       (58.9% logic, 41.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Structure1/HS_1/C_1/Output'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              2.055ns (Levels of Logic = 1)
  Source:            InputA<0> (PAD)
  Destination:       Structure1/R_1/Output_0 (FF)
  Destination Clock: Structure1/HS_1/C_1/Output rising

  Data Path: InputA<0> to Structure1/R_1/Output_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.106   0.681  InputA_0_IBUF (InputA_0_IBUF)
     FDC:D                     0.268          Structure1/R_1/Output_0
    ----------------------------------------
    Total                      2.055ns (1.374ns logic, 0.681ns route)
                                       (66.9% logic, 33.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Structure1/HS_1/C_2/Output'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              2.883ns (Levels of Logic = 2)
  Source:            Carry_In (PAD)
  Destination:       Structure1/FA_1/Output (FF)
  Destination Clock: Structure1/HS_1/C_2/Output rising

  Data Path: Carry_In to Structure1/FA_1/Output
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   1.106   0.897  Carry_In_IBUF (Carry_In_IBUF)
     LUT3:I0->O            1   0.612   0.000  PipeLine_Adder_05_xo<1>1 (Structure1/FA_1/sum<0>)
     FDC:D                     0.268          Structure1/FA_1/Output
    ----------------------------------------
    Total                      2.883ns (1.986ns logic, 0.897ns route)
                                       (68.9% logic, 31.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Structure1/HS_1/C_2/_n0009'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              3.371ns (Levels of Logic = 2)
  Source:            Reset (PAD)
  Destination:       Structure1/HS_1/C_2/Output (LATCH)
  Destination Clock: Structure1/HS_1/C_2/_n0009 falling

  Data Path: Reset to Structure1/HS_1/C_2/Output
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            19   1.106   1.385  Reset_IBUF (Reset_IBUF)
     LUT3:I0->O            1   0.612   0.000  Structure1/HS_1/C_2/_n00011 (Structure1/HS_1/C_2/_n0001)
     LD:D                      0.268          Structure1/HS_1/C_2/Output
    ----------------------------------------
    Total                      3.371ns (1.986ns logic, 1.385ns route)
                                       (58.9% logic, 41.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Structure1/HS_1/C_1/_n0009'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              3.371ns (Levels of Logic = 2)
  Source:            Reset (PAD)
  Destination:       Structure1/HS_1/C_1/Output (LATCH)
  Destination Clock: Structure1/HS_1/C_1/_n0009 falling

  Data Path: Reset to Structure1/HS_1/C_1/Output
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            19   1.106   1.385  Reset_IBUF (Reset_IBUF)
     LUT3_L:I0->LO         1   0.612   0.000  Structure1/HS_1/C_1/_n00011 (Structure1/HS_1/C_1/_n0001)
     LD:D                      0.268          Structure1/HS_1/C_1/Output
    ----------------------------------------
    Total                      3.371ns (1.986ns logic, 1.385ns route)
                                       (58.9% logic, 41.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Structure2/HS_1/C_2/Output'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              4.105ns (Levels of Logic = 1)
  Source:            Structure2/FA_1/Output (FF)
  Destination:       Output<1> (PAD)
  Source Clock:      Structure2/HS_1/C_2/Output rising

  Data Path: Structure2/FA_1/Output to Output<1>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   0.514   0.681  Structure2/FA_1/Output (Structure2/FA_1/Output)
     OBUF:I->O                 2.910          Output_1_OBUF (Output<1>)
    ----------------------------------------
    Total                      4.105ns (3.424ns logic, 0.681ns route)
                                       (83.4% logic, 16.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Structure1/HS_1/C_2/Output'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              4.105ns (Levels of Logic = 1)
  Source:            Structure1/FA_1/Output (FF)
  Destination:       Output<0> (PAD)
  Source Clock:      Structure1/HS_1/C_2/Output rising

  Data Path: Structure1/FA_1/Output to Output<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   0.514   0.681  Structure1/FA_1/Output (Structure1/FA_1/Output)
     OBUF:I->O                 2.910          Output_0_OBUF (Output<0>)
    ----------------------------------------
    Total                      4.105ns (3.424ns logic, 0.681ns route)
                                       (83.4% logic, 16.6% route)

=========================================================================
CPU : 33.48 / 34.22 s | Elapsed : 34.00 / 34.00 s
 
--> 

Total memory usage is 116552 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   12 (   0 filtered)
Number of infos    :    2 (   0 filtered)