pipeline_adder.syr

Self timed pipelined adder

Release 8.1i - xst I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
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--> Reading design: PipeLine_Adder.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "PipeLine_Adder.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "PipeLine_Adder"
Output Format                      : NGC
Target Device                      : xc3s100e-5-vq100

---- Source Options
Top Module Name                    : PipeLine_Adder
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : PipeLine_Adder.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/C_MULLER_GATE.vhd" in Library work.
Architecture behavioral of Entity c_muller_gate is up to date.
Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/Inverter.vhd" in Library work.
Architecture behavioral of Entity inverter is up to date.
Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/Delay_Element.vhd" in Library work.
Architecture behavioral of Entity delay_element is up to date.
Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/Full_Adder.vhd" in Library work.
Architecture behavioral of Entity full_adder is up to date.
Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/Register.vhd" in Library work.
Architecture behavioral of Entity adder_register is up to date.
Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/Hand_Shake.vhd" in Library work.
Architecture structural of Entity hand_shake is up to date.
Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/1_Bit_Pipeline_Adder.vhd" in Library work.
Architecture behavioral of Entity bit_pipeline_adder is up to date.
Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/Two_Delays.vhd" in Library work.
Architecture behavioral of Entity two_delays is up to date.
Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/PipeLine_Adder.vhd" in Library work.
Architecture structural of Entity pipeline_adder is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <PipeLine_Adder> (Architecture <structural>).
Entity <PipeLine_Adder> analyzed. Unit <PipeLine_Adder> generated.

Analyzing Entity <Inverter> (Architecture <behavioral>).
Entity <Inverter> analyzed. Unit <Inverter> generated.

Analyzing Entity <Bit_Pipeline_Adder> (Architecture <behavioral>).
Entity <Bit_Pipeline_Adder> analyzed. Unit <Bit_Pipeline_Adder> generated.

Analyzing Entity <Full_Adder> (Architecture <behavioral>).
Entity <Full_Adder> analyzed. Unit <Full_Adder> generated.

Analyzing Entity <Adder_Register> (Architecture <behavioral>).
Entity <Adder_Register> analyzed. Unit <Adder_Register> generated.

Analyzing Entity <Hand_Shake> (Architecture <structural>).
Entity <Hand_Shake> analyzed. Unit <Hand_Shake> generated.

Analyzing Entity <C_MULLER_GATE> (Architecture <behavioral>).
Entity <C_MULLER_GATE> analyzed. Unit <C_MULLER_GATE> generated.

Analyzing Entity <Two_Delays> (Architecture <behavioral>).
Entity <Two_Delays> analyzed. Unit <Two_Delays> generated.

Analyzing Entity <Delay_Element> (Architecture <behavioral>).
Entity <Delay_Element> analyzed. Unit <Delay_Element> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <Delay_Element>.
    Related source file is "C:/Documents and Settings/People/Desktop/VLSIASS2/Delay_Element.vhd".
Unit <Delay_Element> synthesized.


Synthesizing Unit <C_MULLER_GATE>.
    Related source file is "C:/Documents and Settings/People/Desktop/VLSIASS2/C_MULLER_GATE.vhd".
WARNING:Xst:737 - Found 1-bit latch for signal <Output>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefuly review if it was in your intentions to describe such a latch.
Unit <C_MULLER_GATE> synthesized.


Synthesizing Unit <Hand_Shake>.
    Related source file is "C:/Documents and Settings/People/Desktop/VLSIASS2/Hand_Shake.vhd".
Unit <Hand_Shake> synthesized.


Synthesizing Unit <Adder_Register>.
    Related source file is "C:/Documents and Settings/People/Desktop/VLSIASS2/Register.vhd".
    Found 2-bit register for signal <Output>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <Adder_Register> synthesized.


Synthesizing Unit <Full_Adder>.
    Related source file is "C:/Documents and Settings/People/Desktop/VLSIASS2/Full_Adder.vhd".
    Found 1-bit register for signal <CarryOut>.
    Found 1-bit register for signal <Done>.
    Found 1-bit register for signal <Output>.
    Found 2-bit adder carry in for signal <sum>.
    Summary:
	inferred   3 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <Full_Adder> synthesized.


Synthesizing Unit <Two_Delays>.
    Related source file is "C:/Documents and Settings/People/Desktop/VLSIASS2/Two_Delays.vhd".
Unit <Two_Delays> synthesized.


Synthesizing Unit <Bit_Pipeline_Adder>.
    Related source file is "C:/Documents and Settings/People/Desktop/VLSIASS2/1_Bit_Pipeline_Adder.vhd".
Unit <Bit_Pipeline_Adder> synthesized.


Synthesizing Unit <Inverter>.
    Related source file is "C:/Documents and Settings/People/Desktop/VLSIASS2/Inverter.vhd".
Unit <Inverter> synthesized.


Synthesizing Unit <PipeLine_Adder>.
    Related source file is "C:/Documents and Settings/People/Desktop/VLSIASS2/PipeLine_Adder.vhd".
WARNING:Xst:647 - Input <Acknowledge> is never used.
WARNING:Xst:647 - Input <Request> is never used.
WARNING:Xst:1780 - Signal <Done_3> is never used or assigned.
WARNING:Xst:1780 - Signal <Delay_5_Out> is never used or assigned.
WARNING:Xst:1780 - Signal <Delay_2_Out> is never used or assigned.
WARNING:Xst:1780 - Signal <Delay_3_Out> is never used or assigned.
WARNING:Xst:1780 - Signal <Delay_4_Out> is never used or assigned.
Unit <PipeLine_Adder> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 3
 2-bit adder carry in                                  : 3
# Registers                                            : 12
 1-bit register                                        : 9
 2-bit register                                        : 3
# Latches                                              : 6
 1-bit latch                                           : 6

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 3
 2-bit adder carry in                                  : 3
# Registers                                            : 5
 Flip-Flops                                            : 5
# Latches                                              : 6
 1-bit latch                                           : 6

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Loading device for application Rf_Device from file '3s100e.nph' in environment C:\Xilinx8.1.

Optimizing unit <PipeLine_Adder> ...
WARNING:Xst:1710 - FF/Latch  <Structure3/HS_1/C_2/Output> (without init value) has a constant value of 0 in block <PipeLine_Adder>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <Structure3/FA_1/Done> (without init value) has a constant value of 0 in block <PipeLine_Adder>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <Structure3/FA_1/Output> (without init value) has a constant value of 0 in block <PipeLine_Adder>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <Structure3/FA_1/CarryOut> (without init value) has a constant value of 0 in block <PipeLine_Adder>.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block PipeLine_Adder, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : PipeLine_Adder.ngr
Top Level Output File Name         : PipeLine_Adder
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 15

Cell Usage :
# BELS                             : 15
#      GND                         : 1
#      LUT2                        : 2
#      LUT3                        : 10
#      LUT3_L                      : 1
#      VCC                         : 1
# FlipFlops/Latches                : 14
#      FDC                         : 9
#      LD                          : 5
# IO Buffers                       : 11
#      IBUF                        : 6