bit_pipeline_adder.stx

Self timed pipelined adder

Release 8.1i - xst I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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*                          HDL Compilation                              *
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Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/C_MULLER_GATE.vhd" in Library work.
Architecture behavioral of Entity c_muller_gate is up to date.
Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/Inverter.vhd" in Library work.
Architecture behavioral of Entity inverter is up to date.
Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/Full_Adder.vhd" in Library work.
Architecture behavioral of Entity full_adder is up to date.
Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/Register.vhd" in Library work.
Architecture behavioral of Entity adder_register is up to date.
Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/Hand_Shake.vhd" in Library work.
Architecture structural of Entity hand_shake is up to date.
Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/1_Bit_Pipeline_Adder.vhd" in Library work.
Entity <bit_pipeline_adder> compiled.
Entity <bit_pipeline_adder> (Architecture <behavioral>) compiled.
CPU : 0.30 / 0.85 s | Elapsed : 0.00 / 1.00 s
 
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Total memory usage is 85600 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)