register.vhd

来自「Self timed pipelined adder」· VHDL 代码 · 共 36 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Adder_Register is
    Port ( Input : in  STD_LOGIC_VECTOR (1 downto 0);
           Output : out  STD_LOGIC_VECTOR (1 downto 0);
			  Reset : in STD_LOGIC;
           Enable : in  STD_LOGIC);
end Adder_Register;

architecture Behavioral of Adder_Register is

begin

process(Enable, Reset)
begin
if (Enable'event and Enable ='1') then   
			Output <= Input after 5 ns;
			
end if; 

if (Reset = '1') then
		Output <= "00" after 5 ns;
end if;	
end process;

end Behavioral;