full_adder.vhd

来自「Self timed pipelined adder」· VHDL 代码 · 共 50 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Full_Adder is
    Port ( inA : in STD_LOGIC_VECTOR (1 downto 0);
           inB : in STD_LOGIC_VECTOR (1 downto 0);
           Start : in  STD_LOGIC;
           Done : out  STD_LOGIC;
			  Reset : in STD_LOGIC;
           Output : out  STD_LOGIC;
			  CarryIn : in STD_LOGIC;
			  CarryOut : out STD_LOGIC);
end Full_Adder;

architecture Behavioral of Full_Adder is

signal sum : STD_LOGIC_VECTOR (1 downto 0);

begin
sum <= InA + InB + CarryIn;

process(Start, Reset)
begin
if (Start'event and Start ='1') then  
 			Output <= sum(0) after 10 ns;
			CarryOut <= sum(1) after 10 ns;
			Done <= '1' after 10 ns;
	--else
	--	Done <= '0' after 10 ns; -- changed
		
end if; 

if (Reset = '1') then
		Output <= '0' after 10 ns;
		Done <= '0' after 10 ns;
		CarryOut <= '0' after 10 ns;
end if;	
end process;

end Behavioral;