four_delays.vhd

来自「Self timed pipelined adder」· VHDL 代码 · 共 42 行

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:27:36 05/19/2006 
-- Design Name: 
-- Module Name:    Four_Delays - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Four_Delays is
    Port ( Input : in  STD_LOGIC;
           Output : out  STD_LOGIC);
end Four_Delays;

architecture Behavioral of Four_Delays is

begin


end Behavioral;