tb_pipeline_adder.tbw

Self timed pipelined adder

version 3
C:/Documents and Settings/People/Desktop/VLSIASS2/PipeLine_Adder.vhd
PipeLine_Adder
VHDL
VHDL
TB_Pipeline_Adder.xwv
Comb
50000000
50000000
10000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
Done_DIFF
Output_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
Reset
Request
Acknowledge
InputA
InputB
Output
Carry_In
Done
SIGNAL_ORDER_END
-X-X-X-