hdllib.ref

来自「Self timed pipelined adder」· REF 代码 · 共 13 行

AR adder_register behavioral "C:/Documents and Settings/TOBY LI/My Documents/BT/VLSI Assignment 2/VLSIASS2/Register.vhd" sub00/vhpl01 1179693525
EN bit_pipeline_adder NULL "C:/Documents and Settings/TOBY LI/My Documents/BT/VLSI Assignment 2/VLSIASS2/1_Bit_Pipeline_Adder.vhd" sub00/vhpl10 1179693532
EN inverter NULL "C:/Documents and Settings/TOBY LI/My Documents/BT/VLSI Assignment 2/VLSIASS2/Inverter.vhd" sub00/vhpl04 1179693542
AR inverter behavioral "C:/Documents and Settings/TOBY LI/My Documents/BT/VLSI Assignment 2/VLSIASS2/Inverter.vhd" sub00/vhpl05 1179693543
EN hand_shake NULL "C:/Documents and Settings/TOBY LI/My Documents/BT/VLSI Assignment 2/VLSIASS2/Hand_Shake.vhd" sub00/vhpl08 1179693544
EN adder_register NULL "C:/Documents and Settings/TOBY LI/My Documents/BT/VLSI Assignment 2/VLSIASS2/Register.vhd" sub00/vhpl00 1179693524
AR full_adder behavioral "C:/Documents and Settings/TOBY LI/My Documents/BT/VLSI Assignment 2/VLSIASS2/Full_Adder.vhd" sub00/vhpl07 1179693527
EN full_adder NULL "C:/Documents and Settings/TOBY LI/My Documents/BT/VLSI Assignment 2/VLSIASS2/Full_Adder.vhd" sub00/vhpl06 1179693526
AR c_muller_gate behavioral "C:/Documents and Settings/TOBY LI/My Documents/BT/VLSI Assignment 2/VLSIASS2/C_MULLER_GATE.vhd" sub00/vhpl03 1179693541
AR hand_shake structural "C:/Documents and Settings/TOBY LI/My Documents/BT/VLSI Assignment 2/VLSIASS2/Hand_Shake.vhd" sub00/vhpl09 1179693545
AR bit_pipeline_adder behavioral "C:/Documents and Settings/TOBY LI/My Documents/BT/VLSI Assignment 2/VLSIASS2/1_Bit_Pipeline_Adder.vhd" sub00/vhpl11 1179693533
EN c_muller_gate NULL "C:/Documents and Settings/TOBY LI/My Documents/BT/VLSI Assignment 2/VLSIASS2/C_MULLER_GATE.vhd" sub00/vhpl02 1179693540