tb_adder_register.tbw

Self timed pipelined adder

version 3
C:/Documents and Settings/People/Desktop/VLSIASS2/Register.vhd
Adder_Register
VHDL
VHDL
TB_Adder_Register.xwv
Comb
50000000
50000000
1000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
Output_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
SIGNAL_ORDER_END
-X-X-X-