enableandstart.stx

来自「Self timed pipelined adder」· STX 代码 · 共 27 行

Release 8.1i - xst I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.56 s | Elapsed : 0.00 / 0.00 s
 
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=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/Full_Adder.vhd" in Library work.
Architecture behavioral of Entity full_adder is up to date.
Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/Register.vhd" in Library work.
Architecture behavioral of Entity adder_register is up to date.
Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/EnableAndStart.vhd" in Library work.
Entity <enableandstart> compiled.
Entity <enableandstart> (Architecture <behavioral>) compiled.
CPU : 0.23 / 0.79 s | Elapsed : 1.00 / 1.00 s
 
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Total memory usage is 85600 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)