pipeline_adder.vhd

Self timed pipelined adder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity PipeLine_Adder is
    Port (InputA : in STD_LOGIC_VECTOR (2 downto 0);
			 InputB : in STD_LOGIC_VECTOR (2 downto 0);
			 Request : in STD_LOGIC;
			 Acknowledge : in STD_LOGIC;
			 Reset : in STD_LOGIC;
			 Carry_In : in STD_LOGIC;
			 Done : out STD_LOGIC;
			 Output : out STD_LOGIC_VECTOR (3 downto 0)
		    );
end PipeLine_Adder;

architecture Structural of PipeLine_Adder is

COMPONENT Bit_Pipeline_Adder
		Port ( InputA : in  STD_LOGIC;
			  InputB : in STD_LOGIC;
           Req : in  STD_LOGIC;
           Output : out  STD_LOGIC;
           Carry_Out : out  STD_LOGIC;
			  Carry_In : in STD_LOGIC;
           Done : out  STD_LOGIC;
           RecAck : in  STD_LOGIC:= '1';
           SendAck : out  STD_LOGIC;
			  Reset : in STD_LOGIC);
End COMPONENT;

COMPONENT Two_Delays
		Port ( Input : in STD_LOGIC;
				Output : out STD_LOGIC);
End COMPONENT;

COMPONENT Inverter
	PORT ( Input : in STD_LOGIC;
			 Output : out STD_LOGIC);
End Component;

signal Done_1 : STD_LOGIC;
signal Done_2 : STD_LOGIC;
signal Done_3 : STD_LOGIC;
signal Carry_Out_1 : STD_LOGIC;
signal Carry_Out_2 : STD_LOGIC;
signal SendAck_1 : STD_LOGIC;
signal SendAck_2 : STD_LOGIC;
signal SendAck_3 : STD_LOGIC;
signal FA_1_Out : STD_LOGIC;
signal FA_2_Out : STD_LOGIC;
signal Delay_1_Out : STD_LOGIC;
signal Delay_2_Out : STD_LOGIC;
signal Delay_3_Out : STD_LOGIC;
signal Delay_4_Out : STD_LOGIC;
signal Delay_5_Out : STD_LOGIC;
signal not_SendAck_1 : STD_LOGIC;

begin

Start_Inverter: Inverter

	Port Map(Input => SendAck_1,
				Output => Not_SendAck_1);

Structure1: Bit_Pipeline_Adder

	Port Map( InputA => InputA(0),
			  InputB => InputB(0),
           Req => Not_SendAck_1,
           Output => FA_1_Out,
           Carry_Out => Carry_Out_1,
			  Carry_In => Carry_In,
           Done => Done_1,
           RecAck => SendAck_2,
           SendAck => SendAck_1,
			  Reset => Reset);
			  
Two_Delay1: Two_Delays

	Port Map( Input => FA_1_Out,
				Output => Delay_1_Out);
				
Two_Delay2: Two_Delays

	Port Map( Input => Delay_1_Out,
				Output => Output(0));

Structure2: Bit_Pipeline_Adder

	Port Map( InputA => InputA(1),
			  InputB => InputB(1),
           Req => Done_1,
           Output => FA_2_Out,
           Carry_Out => Carry_Out_2,
			  Carry_In => Carry_Out_1,
           Done => Done_2,
           RecAck => SendAck_3,
           SendAck => SendAck_2,
			  Reset => Reset);
			  
Two_Delay3: Two_Delays

	Port Map( Input => FA_2_Out,
				Output => Output(1));
			  
Structure3: Bit_Pipeline_Adder

	Port Map( InputA => InputA(2),
			  InputB => InputB(2),
           Req => Done_2,
           Output => Output(2),
           Carry_Out => Output(3),
			  Carry_In => Carry_Out_2,
           Done => Done,
           RecAck => SendAck_3, 
           SendAck => SendAck_3,
			  Reset => Reset);
			  
		  
end Structural;