c_muller_gate.vhd

来自「Self timed pipelined adder」· VHDL 代码 · 共 40 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity C_MULLER_GATE is
    Port ( C_Input : in  STD_LOGIC_VECTOR (1 downto 0);
           Reset : in  STD_LOGIC;
           Output : out  STD_LOGIC);
end C_MULLER_GATE;

architecture Behavioral of C_MULLER_GATE is

begin

process(Reset, C_Input)
begin

case C_Input is 
      when "00" =>
         Output <= '0' after 5 ns;
      when "11" =>
         Output <= '1' after 5 ns;
		when others =>
			null;
end case;
	
if (Reset = '1') then
		Output <= '0' after 5 ns;
end if;	
end process;			

end Behavioral;