1_bit_pipeline_adder.stx

来自「Self timed pipelined adder」· STX 代码 · 共 32 行

Release 8.1i - xst I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/C_MULLER_GATE.vhd" in Library work.
Architecture behavioral of Entity c_muller_gate is up to date.
Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/Inverter.vhd" in Library work.
Architecture behavioral of Entity inverter is up to date.
Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/Full_Adder.vhd" in Library work.
Architecture behavioral of Entity full_adder is up to date.
Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/Register.vhd" in Library work.
Architecture behavioral of Entity adder_register is up to date.
Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/Hand_Shake.vhd" in Library work.
Architecture structural of Entity hand_shake is up to date.
Compiling vhdl file "C:/Documents and Settings/People/Desktop/VLSIASS2/1_Bit_Pipeline_Adder.vhd" in Library work.
ERROR:HDLParsers:164 - "C:/Documents and Settings/People/Desktop/VLSIASS2/1_Bit_Pipeline_Adder.vhd" Line 30. parse error, unexpected INTEGER_LITERAL, expecting IDENTIFIER
CPU : 0.78 / 2.53 s | Elapsed : 1.00 / 3.00 s
 
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Total memory usage is 85600 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)