1_bit_pipeline_adder_vhdl.prj

来自「Self timed pipelined adder」· PRJ 代码 · 共 7 行

PRJ
7 行
字号 
work "C:\Documents and Settings\People\Desktop\VLSIASS2\Inverter.vhd"
work "C:\Documents and Settings\People\Desktop\VLSIASS2\C_MULLER_GATE.vhd"
work "C:\Documents and Settings\People\Desktop\VLSIASS2\Register.vhd"
work "C:\Documents and Settings\People\Desktop\VLSIASS2\Hand_Shake.vhd"
work "C:\Documents and Settings\People\Desktop\VLSIASS2\Full_Adder.vhd"
work "C:\Documents and Settings\People\Desktop\VLSIASS2\1_Bit_Pipeline_Adder.vhd"

1_bit_pipeline_adder_vhdl.prj - 源码说明

本页面展示了「Self timed pipelined adder」中的 1_bit_pipeline_adder_vhdl.prj 源码文件，采用 PRJ 编程语言编写，共 7 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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