tb_full_adder.ado

Self timed pipelined adder

source {C:/Xilinx8.1/data/projnav/scripts/VsimStopServer.tcl}
-- Auto Generated by Project Navigator to simulate
-- HDL Bencher Annotated Test Bench
--
vlib work
onbreak {resume}
onerror {quit -code 99 -force}
onElabError {resume}
vcom -explicit  -93 Full_Adder.vhd
vcom -explicit  -93 "TB_Full_Adder.ant"
vsim -t 1ps   -lib work TB_Full_Adder
run -all
quit -force