📄 lcd.vhd
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--/*LCD．VHD*/--LCD驱动模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lcd is
-- generic (N:integer:=32000;
-- delay:integer:=20);
Port (clk,rst:in std_logic;
rs,wr,e:out std_logic;
data:inout std_logic_vector(7 downto 0);
pl:in std_logic_vector(31 downto 0);
d:in integer range -10 to 10);
end lcd;
architecture Behavioral of lcd is
type state is (set_dlnf,clear_lcd,set_cursor,set_dcb,set_location,
write_data,set_location1,write_data1,
set_location4,write_data4,set_location5,write_data5,
set_location6,write_data6,set_location7,write_data7);
signal current_state:state;
type rom is array(0 to 15) of std_logic_vector(7 downto 0);
type rom1 is array(0 to 11) of std_logic_vector(7 downto 0);
type rom2 is array(0 to 2) of std_logic_vector(7 downto 0);
constant datarom:rom:=(("00100000"),("00101010"),("00101010"),("01000011"),("01111001"),("01101101"),("01101111"),("01101101"),("01100101"),("01110100"),("01100101"),("01110010"),("00101010"),("00101010"),("00100000"),("00100000"));
constant datarom1:rom1:=(("00110000"),("00110001"),("00110010"),("00110011"),("00110100"),("00110101"),("00110110"),("00110111"),("00111000"),("00111001"),("00101110"),("00100000"));--0123456789.空格 点:10100101
constant datarom2:rom2:=(("00100000"),("01001000"),("01111010"));
signal clkk:std_logic;
signal dd:integer range 0 to 10;
constant N:integer :=3200;--3200
constant delay:integer :=20;--20
signal zz,zz1:integer range 0 to 2;
signal i:integer range 0 to 9;
signal cnt3:integer range 0 to 7;
begin
process(cnt3)
begin
case cnt3 is
when 0=>i<=conv_integer(pl(31 downto 28));
when 1=>i<=conv_integer(pl(27 downto 24));
when 2=>i<=conv_integer(pl(23 downto 20));
when 3=>i<=conv_integer(pl(19 downto 16));
when 4=>i<=conv_integer(pl(15 downto 12));
when 5=>i<=conv_integer(pl(11 downto 8));
when 6=>i<=conv_integer(pl(7 downto 4));
when 7=>i<=conv_integer(pl(3 downto 0));
end case;
end process;
process(d,pl)
begin
if d<=-1 then
dd<=2;zz<=2;
elsif d<=0 then
dd<=2;zz<=1;
elsif d<=10 then
if pl/=0 then
dd<=d+1;zz<=0;
else
dd<=2;zz<=1;
end if;
else
dd<=0;zz<=0;
end if;
end process;
process(rst,clk)
variable cnt:integer;
begin
if rst='0' then
cnt:=0;clkk<='0';
elsif rising_edge(clk) then
cnt:=cnt+1;
if cnt<N then
clkk<='0';
else
clkk<='1';
end if;
if cnt>=2*N then
cnt:=0;
end if;
end if;
end process;
process(rst,clkk,current_state)
variable cntt,cnt2:integer;
begin
if rst='0' then
current_state<=set_dlnf;
cntt:=0;cnt2:=0;cnt3<=0;
elsif rising_edge(clkk) then
case current_state is
when set_dlnf=>rs<='0';wr<='0';e<='0';
data<="00111000";
cntt:=cntt+1;
if cntt>delay and cntt<=delay*2 then
e<='1';
else
e<='0';
end if;
if cntt>=3*delay then
current_state<=clear_lcd;
cntt:=0;
end if;
when clear_lcd=>rs<='0';wr<='0';e<='0';
data<="00000001";
cntt:=cntt+1;
if cntt>delay*3 and cntt<delay*6 then
e<='1';
else
e<='0';
end if;
if cntt>=delay*9 then
current_state<=set_cursor;
cntt:=0;
end if;
when set_cursor=>rs<='0';wr<='0';e<='0';
data<="00000110";
cntt:=cntt+1;
if cntt>delay and cntt<delay*2 then
e<='1';
else
e<='0';
end if;
if cntt>=delay*3 then
current_state<=set_dcb;
cntt:=0;
end if;
when set_dcb=>rs<='0';wr<='0';e<='0';
data<="00001100";
cntt:=cntt+1;
if cntt>delay and cntt<delay*2 then
e<='1';
else
e<='0';
end if;
if cntt>=delay*3 then
current_state<=set_location;
cntt:=0;
end if;
when set_location=>rs<='0';wr<='0';e<='0';
data<="10000000";
cntt:=cntt+1;
if cntt>delay and cntt<delay*2 then
e<='1';
else
e<='0';
end if;
if cntt>=delay*3 then
current_state<=write_data;
cntt:=0;
end if;
when write_data=>rs<='1';wr<='0';e<='0';
if cnt2<=15 then
data<=datarom(cnt2);
cntt:=cntt+1;
if cntt>delay and cntt<delay*2 then
e<='1';
else
e<='0';
end if;
if cntt>=delay*3 then
current_state<=write_data;
cntt:=0;
cnt2:=cnt2+1;
end if;
else
cnt2:=0;
current_state<=set_location1;
end if;
when set_location1=>rs<='0';wr<='0';e<='0';
data<="11001101";
cntt:=cntt+1;
if cntt>delay and cntt<delay*2 then
e<='1';
else
e<='0';
end if;
if cntt>=delay*3 then
current_state<=write_data1;
cntt:=0;
end if;
when write_data1=>rs<='1';wr<='0';e<='0';
if cnt2<=2 then
data<=datarom2(cnt2);
cntt:=cntt+1;
if cntt>delay and cntt<delay*2 then
e<='1';
else
e<='0';
end if;
if cntt>=delay*3 then
current_state<=write_data1;
cntt:=0;
cnt2:=cnt2+1;
end if;
else
cnt2:=0;
current_state<=set_location4;
end if;
when set_location4=>rs<='0';wr<='0';e<='0';
data<="11000000";
cntt:=cntt+1;
if cntt>delay and cntt<delay*2 then
e<='1';
else
e<='0';
end if;
if cntt>=delay*3 then
current_state<=write_data4;
cntt:=0;
end if;
when write_data4=>rs<='1';wr<='0';e<='0';
if cnt2<=3-zz then --13-(8+zz+1)-1
data<=datarom1(11);
cntt:=cntt+1;
if cntt>delay and cntt<delay*2 then
e<='1';
else
e<='0';
end if;
if cntt>=delay*3 then
current_state<=write_data4;
cntt:=0;
cnt2:=cnt2+1;
end if;
else
cnt2:=0;
current_state<=set_location5;
end if;
when set_location5=>rs<='0';wr<='0';e<='0';
data<="11000100"-conv_std_logic_vector(zz,8);
cntt:=cntt+1;
if cntt>delay and cntt<delay*2 then
e<='1';
else
e<='0';
end if;
if cntt>=delay*3 then
current_state<=write_data5;
cntt:=0;
zz1<=zz;
cnt3<=0;
end if;
when write_data5=>
if cnt2<dd-1 then
if zz1>0 then
data<=datarom1(0);
else
data<=datarom1(i);
end if;
rs<='1';wr<='0';e<='0';
cntt:=cntt+1;
if cntt>delay and cntt<delay*2 then
e<='1';
else
e<='0';
end if;
if cntt>=delay*3 then
current_state<=write_data5;
cntt:=0;
cnt2:=cnt2+1;
if zz1=0 then
cnt3<=cnt3+1;
else
zz1<=zz1-1;
end if;
end if;
else
cnt2:=0;
current_state<=set_location6;
end if;
when set_location6=>rs<='0';wr<='0';e<='0';
data<="11000011"+conv_std_logic_vector((dd-zz),8);
cntt:=cntt+1;
if cntt>delay and cntt<delay*2 then
e<='1';
else
e<='0';
end if;
if cntt>=delay*3 then
current_state<=write_data6;
cntt:=0;
end if;
when write_data6=>rs<='1';wr<='0';e<='0';
if cnt2<=0 then
data<=datarom1(10);
cntt:=cntt+1;
if cntt>delay and cntt<delay*2 then
e<='1';
else
e<='0';
end if;
if cntt>=delay*3 then
current_state<=write_data6;
cntt:=0;
cnt2:=cnt2+1;
end if;
else
cnt2:=0;
current_state<=set_location7;
end if;
when set_location7=>rs<='0';wr<='0';e<='0';
data<="11000100"+conv_std_logic_vector((dd-zz),8);
cntt:=cntt+1;
if cntt>delay and cntt<delay*2 then
e<='1';
else
e<='0';
end if;
if cntt>=delay*3 then
current_state<=write_data7;
cntt:=0;
end if;
when write_data7=>rs<='1';wr<='0';e<='0';
if cnt2<=8+zz-dd then
if zz1>0 then
data<=datarom1(0);
else
data<=datarom1(i);
end if;
cntt:=cntt+1;
if cntt>delay and cntt<delay*2 then
e<='1';
else
e<='0';
end if;
if cntt>=delay*3 then
current_state<=write_data7;
cntt:=0;
cnt2:=cnt2+1;
if zz1=0 then
if cnt3<=6 then
cnt3<=cnt3+1;
end if;
else
zz1<=zz1-1;
end if;
end if;
else
cnt2:=0;
current_state<=set_location;
end if;
end case;
end if;
end process;
end Behavioral;
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