djdplj_top.map.qmsg

用QUARTUS编译通过的等精度频率计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 20 17:10:12 2007 " "Info: Processing started: Sun May 20 17:10:12 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off djdplj_top -c djdplj_top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off djdplj_top -c djdplj_top" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "djdplj_top.vhd 2 1 " "Warning: Using design file djdplj_top.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 djdplj_top-Behavioral " "Info: Found design unit 1: djdplj_top-Behavioral" {  } { { "djdplj_top.vhd" "" { Text "C:/FJASLDF/djdplj_top.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 djdplj_top " "Info: Found entity 1: djdplj_top" {  } { { "djdplj_top.vhd" "" { Text "C:/FJASLDF/djdplj_top.vhd" 12 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "djdplj_top " "Info: Elaborating entity \"djdplj_top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "dc1 djdplj_top.vhd(91) " "Warning (10631): VHDL Process Statement warning at djdplj_top.vhd(91): inferring latch(es) for signal or variable \"dc1\", which holds its previous value in one or more paths through the process" {  } { { "djdplj_top.vhd" "" { Text "C:/FJASLDF/djdplj_top.vhd" 91 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "dc1 djdplj_top.vhd(91) " "Info (10041): Verilog HDL or VHDL info at djdplj_top.vhd(91): inferred latch for \"dc1\"" {  } { { "djdplj_top.vhd" "" { Text "C:/FJASLDF/djdplj_top.vhd" 91 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "cepin.vhd 2 1 " "Warning: Using design file cepin.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cepin-Behavioral " "Info: Found design unit 1: cepin-Behavioral" {  } { { "cepin.vhd" "" { Text "C:/FJASLDF/cepin.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 cepin " "Info: Found entity 1: cepin" {  } { { "cepin.vhd" "" { Text "C:/FJASLDF/cepin.vhd" 12 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cepin cepin:u1 " "Info: Elaborating entity \"cepin\" for hierarchy \"cepin:u1\"" {  } { { "djdplj_top.vhd" "u1" { Text "C:/FJASLDF/djdplj_top.vhd" 55 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "div.vhd 2 1 " "Warning: Using design file div.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div-Behavioral " "Info: Found design unit 1: div-Behavioral" {  } { { "div.vhd" "" { Text "C:/FJASLDF/div.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 div " "Info: Found entity 1: div" {  } { { "div.vhd" "" { Text "C:/FJASLDF/div.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div div:u2 " "Info: Elaborating entity \"div\" for hierarchy \"div:u2\"" {  } { { "djdplj_top.vhd" "u2" { Text "C:/FJASLDF/djdplj_top.vhd" 56 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Error" "EVRFX_VHDL_LEFT_BOUND_OF_RANGE_NOT_CONSTANT" "div.vhd(57) " "Error (10394): VHDL error at div.vhd(57): left bound of range must be a constant" {  } { { "div.vhd" "" { Text "C:/FJASLDF/div.vhd" 57 0 0 } }  } 0 10394 "VHDL error at %1!s!: left bound of range must be a constant" 0 0}
{ "Error" "EVRFX_VHDL_FORMAL_HAS_NO_VALUE" "L syn_unsi.vhd(114) " "Error (10346): VHDL error at syn_unsi.vhd(114): formal port or parameter \"L\" must have actual or default value" {  } { { "d:/quartus70_windows/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/quartus70_windows/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 114 0 0 } }  } 0 10346 "VHDL error at %2!s!: formal port or parameter \"%1!s!\" must have actual or default value" 0 0}
{ "Error" "EVRFX_VHDL_2047_UNCONVERTED" "range syn_unsi.vhd(115) " "Error (10809): VHDL error at syn_unsi.vhd(115): prefix for attribute range must denote a constrained array type" {  } { { "d:/quartus70_windows/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/quartus70_windows/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 115 0 0 } }  } 0 10809 "VHDL error at %2!s!: prefix for attribute %1!s! must denote a constrained array type" 0 0}
{ "Error" "EVRFX_VHDL_OPERATOR_CALL_FAILED" "\"+\" div.vhd(57) " "Error (10658): VHDL Operator error at div.vhd(57): failed to evaluate call to operator \"\"+\"\"" {  } { { "div.vhd" "" { Text "C:/FJASLDF/div.vhd" 57 0 0 } }  } 0 10658 "VHDL Operator error at %2!s!: failed to evaluate call to operator \"%1!s!\"" 0 0}
{ "Error" "EVRFX_VHDL_FORMAL_HAS_NO_VALUE" "L syn_unsi.vhd(239) " "Error (10346): VHDL error at syn_unsi.vhd(239): formal port or parameter \"L\" must have actual or default value" {  } { { "d:/quartus70_windows/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/quartus70_windows/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 239 0 0 } }  } 0 10346 "VHDL error at %2!s!: formal port or parameter \"%1!s!\" must have actual or default value" 0 0}
{ "Error" "EVRFX_VHDL_FORMAL_HAS_NO_VALUE" "R syn_unsi.vhd(239) " "Error (10346): VHDL error at syn_unsi.vhd(239): formal port or parameter \"R\" must have actual or default value" {  } { { "d:/quartus70_windows/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/quartus70_windows/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 239 0 0 } }  } 0 10346 "VHDL error at %2!s!: formal port or parameter \"%1!s!\" must have actual or default value" 0 0}
{ "Error" "EVRFX_VHDL_OPERATOR_CALL_FAILED" "\">=\" div.vhd(57) " "Error (10658): VHDL Operator error at div.vhd(57): failed to evaluate call to operator \"\">=\"\"" {  } { { "div.vhd" "" { Text "C:/FJASLDF/div.vhd" 57 0 0 } }  } 0 10658 "VHDL Operator error at %2!s!: failed to evaluate call to operator \"%1!s!\"" 0 0}
{ "Error" "ESGN_USER_HIER_ELABORATION_FAILURE" "div:u2 " "Error: Can't elaborate user hierarchy \"div:u2\"" {  } { { "djdplj_top.vhd" "u2" { Text "C:/FJASLDF/djdplj_top.vhd" 56 0 0 } }  } 0 0 "Can't elaborate user hierarchy \"%1!s!\"" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 8 s 4 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 8 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "133 " "Info: Allocated 133 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Error" "EQEXE_END_BANNER_TIME" "Sun May 20 17:10:17 2007 " "Error: Processing ended: Sun May 20 17:10:17 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:05 " "Error: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}