djdplj_top.vhd

用QUARTUS编译通过的等精度频率计

--/* DJDPLJ_TOP．VHD*/--顶层模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity djdplj_top is
    Port (rst,clk:in std_logic;
	 		 dc,das:in std_logic;
	 		 rs,wr,e:out std_logic;
			 lcd_data:inout std_logic_vector(7 downto 0));
end djdplj_top;

architecture Behavioral of djdplj_top is

component cepin is
    Port (bz:in std_logic;
	 		 dc:in std_logic;
			 rst,cl:in std_logic;
			 bzclk,dcclk:out std_logic_vector(31 downto 0));
end component cepin;

component div is
    Port (clk,rst:in std_logic;
	 		 bei,chu:in std_logic_vector(31 downto 0);
			 shang:out std_logic_vector(31 downto 0);
			 dian:out integer range -10 to 10 );
end component div;

component lcd is
    Port (clk,rst:in std_logic;
	 		 rs,wr,e:out std_logic;
			 data:inout std_logic_vector(7 downto 0);
			 pl:in std_logic_vector(31 downto 0);
			 d:in integer range -10 to 10);
end component lcd;

component reset is
    Port (clk,rst:in std_logic;
	 		 cl,clr:out std_logic );
end component reset;

signal rst1,cl1,clr1,clkk:std_logic;
signal bzclk1,dcclk1,shang1:std_logic_vector(31 downto 0);
signal dian1:integer range -10 to 10;
signal dc1:std_logic;

begin

u1:cepin port map(bz=>clkk,dc=>dc1,rst=>clr1,cl=>cl1,bzclk=>bzclk1,dcclk=>dcclk1);
u2:div   port map(clk=>clk,rst=>rst1,bei=>dcclk1,chu=>bzclk1,shang=>shang1,dian=>dian1);
u3:lcd   port map(clk=>clk,rst=>rst1,rs=>rs,wr=>wr,e=>e,data=>lcd_data,pl=>shang1,d=>dian1);
u4:reset port map(clk=>clk,rst=>rst1,cl=>cl1,clr=>clr1);

process(clk,rst)
variable cnt:integer range 0 to 15;
begin
	if rst='0' then
		cnt:=0;clkk<='0';
	elsif rising_edge(clk) then
		if cnt=15 then
			cnt:=0;clkk<=not clkk;
		else
			cnt:=cnt+1;
		end if;
	end if;
end process;
process(clk,rst)
variable cnt:integer range 0 to 3200000;
begin
	if rst='0' then
		cnt:=0;
	elsif rising_edge(clk) then
		if cnt<=10000 then
			cnt:=cnt+1;
			rst1<='1';
		elsif cnt<=20000 then
			cnt:=cnt+1;
			rst1<='0';
		else
			cnt:=30000;
			rst1<=rst;
		end if;
	end if;
end process;
process(das,dc)
begin
	if das='0' then
		dc1<=dc;
	end if;
end process;

end Behavioral;